arch/arm/cpu/armv7/omap5/hw_data.c

   1 /*
   2  *
   3  * HW data initialization for OMAP5
   4  *
   5  * (C) Copyright 2013
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Sricharan R <r.sricharan@ti.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12 #include <common.h>
  13 #include <palmas.h>
  14 #include <asm/arch/omap.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/omap_gpio.h>
  19 #include <asm/io.h>
  20 #include <asm/emif.h>
  21
  22 struct prcm_regs const **prcm =
  23                         (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
  24 struct dplls const **dplls_data =
  25                         (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
  26 struct vcores_data const **omap_vcores =
  27                 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
  28 struct omap_sys_ctrl_regs const **ctrl =
  29         (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
  30
  31 /* OPP HIGH FREQUENCY for ES2.0 */
  32 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
  33         {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  34         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  35         {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
  36         {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  37         {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  38         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  39         {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  40 };
  41
  42 /* OPP NOM FREQUENCY for ES1.0 */
  43 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
  44         {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  45         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  46         {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 16.8 MHz */
  47         {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  48         {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  49         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  50         {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  51 };
  52
  53 /* OPP LOW FREQUENCY for ES1.0 */
  54 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
  55         {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  56         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  57         {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 16.8 MHz */
  58         {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  59         {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  60         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  61         {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  62 };
  63
  64 /* OPP LOW FREQUENCY for ES2.0 */
  65 static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
  66         {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
  67         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  68         {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
  69         {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
  70         {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  71         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  72         {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  73 };
  74
  75 /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
  76 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
  77         {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
  78         {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz   */
  79         {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
  80         {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  81         {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 26 MHz   */
  82         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  83         {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 38.4 MHz */
  84 };
  85
  86 static const struct dpll_params
  87                         core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
  88         {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 12 MHz   */
  89         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  90         {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 16.8 MHz */
  91         {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 19.2 MHz */
  92         {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 26 MHz   */
  93         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  94         {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}               /* 38.4 MHz */
  95 };
  96
  97 static const struct dpll_params
  98                         core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
  99         {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 12 MHz   */
 100         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 101         {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 16.8 MHz */
 102         {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 19.2 MHz */
 103         {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 26 MHz   */
 104         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 105         {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}                /* 38.4 MHz */
 106 };
 107
 108 static const struct dpll_params
 109                 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
 110         {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 12 MHz   */
 111         {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 20 MHz   */
 112         {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 16.8 MHz */
 113         {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 19.2 MHz */
 114         {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 26 MHz   */
 115         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 116         {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 38.4 MHz */
 117 };
 118
 119 static const struct dpll_params
 120                         core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
 121         {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 12 MHz   */
 122         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 123         {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 16.8 MHz */
 124         {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 19.2 MHz */
 125         {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 26 MHz   */
 126         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 127         {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}            /* 38.4 MHz */
 128 };
 129
 130 static const struct dpll_params
 131                         core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
 132         {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 12 MHz   */
 133         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 134         {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 16.8 MHz */
 135         {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 19.2 MHz */
 136         {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 26 MHz   */
 137         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 138         {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}             /* 38.4 MHz */
 139 };
 140
 141 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
 142         {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},             /* 12 MHz   */
 143         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 144         {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},            /* 16.8 MHz */
 145         {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},             /* 19.2 MHz */
 146         {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},           /* 26 MHz   */
 147         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 148         {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}              /* 38.4 MHz */
 149 };
 150
 151 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 152         {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},             /* 12 MHz   */
 153         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 154         {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},            /* 16.8 MHz */
 155         {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},             /* 19.2 MHz */
 156         {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},           /* 26 MHz   */
 157         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 158         {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}              /* 38.4 MHz */
 159 };
 160
 161 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
 162         {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 12 MHz   */
 163         {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 20 MHz   */
 164         {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},             /* 16.8 MHz */
 165         {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 19.2 MHz */
 166         {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},            /* 26 MHz   */
 167         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 168         {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 38.4 MHz */
 169 };
 170
 171 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
 172         {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 173         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 174         {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
 175         {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 176         {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 177         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 178         {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}           /* 38.4 MHz */
 179 };
 180
 181 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
 182         {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 183         {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz */
 184         {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
 185         {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 186         {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 187         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 188         {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 38.4 MHz */
 189 };
 190
 191 /* ABE M & N values with sys_clk as source */
 192 static const struct dpll_params
 193                 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
 194         {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
 195         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 196         {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
 197         {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 19.2 MHz */
 198         {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 26 MHz   */
 199         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 200         {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}          /* 38.4 MHz */
 201 };
 202
 203 /* ABE M & N values with 32K clock as source */
 204 static const struct dpll_params abe_dpll_params_32k_196608khz = {
 205         750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
 206 };
 207
 208 /* ABE M & N values with sysclk2(22.5792 MHz) as input */
 209 static const struct dpll_params
 210                 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
 211         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 212         {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
 213         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 16.8 MHz */
 214         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
 215         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
 216         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 217         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
 218 };
 219
 220 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
 221         {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
 222         {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 20 MHz   */
 223         {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
 224         {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
 225         {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
 226         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 227         {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
 228 };
 229
 230 static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
 231         {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 12 MHz   */
 232         {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
 233         {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
 234         {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 19.2 MHz */
 235         {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 236         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 237         {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 38.4 MHz */
 238 };
 239
 240 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
 241         {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 12 MHz   */
 242         {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
 243         {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
 244         {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 245         {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 246         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 247         {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 38.4 MHz */
 248 };
 249
 250 static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
 251         {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},         /* 12 MHz   */
 252         {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},         /* 20 MHz   */
 253         {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},         /* 16.8 MHz */
 254         {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},        /* 19.2 MHz */
 255         {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},        /* 26 MHz   */
 256         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 257         {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},        /* 38.4 MHz */
 258 };
 259
 260 struct dplls omap5_dplls_es1 = {
 261         .mpu = mpu_dpll_params_800mhz,
 262         .core = core_dpll_params_2128mhz_ddr532,
 263         .per = per_dpll_params_768mhz,
 264         .iva = iva_dpll_params_2330mhz,
 265 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 266         .abe = abe_dpll_params_sysclk_196608khz,
 267 #else
 268         .abe = &abe_dpll_params_32k_196608khz,
 269 #endif
 270         .usb = usb_dpll_params_1920mhz,
 271         .ddr = NULL
 272 };
 273
 274 struct dplls omap5_dplls_es2 = {
 275         .mpu = mpu_dpll_params_1ghz,
 276         .core = core_dpll_params_2128mhz_ddr532_es2,
 277         .per = per_dpll_params_768mhz_es2,
 278         .iva = iva_dpll_params_2330mhz,
 279 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 280         .abe = abe_dpll_params_sysclk_196608khz,
 281 #else
 282         .abe = &abe_dpll_params_32k_196608khz,
 283 #endif
 284         .usb = usb_dpll_params_1920mhz,
 285         .ddr = NULL
 286 };
 287
 288 struct dplls dra7xx_dplls = {
 289         .mpu = mpu_dpll_params_1ghz,
 290         .core = core_dpll_params_2128mhz_dra7xx,
 291         .per = per_dpll_params_768mhz_dra7xx,
 292         .abe = abe_dpll_params_sysclk2_361267khz,
 293         .iva = iva_dpll_params_2330mhz_dra7xx,
 294         .usb = usb_dpll_params_1920mhz,
 295         .ddr = ddr_dpll_params_2128mhz,
 296         .gmac = gmac_dpll_params_2000mhz,
 297 };
 298
 299 struct dplls dra72x_dplls = {
 300         .mpu = mpu_dpll_params_1ghz,
 301         .core = core_dpll_params_2128mhz_dra7xx,
 302         .per = per_dpll_params_768mhz_dra7xx,
 303         .abe = abe_dpll_params_sysclk2_361267khz,
 304         .iva = iva_dpll_params_2330mhz_dra7xx,
 305         .usb = usb_dpll_params_1920mhz,
 306         .ddr =  ddr_dpll_params_2664mhz,
 307         .gmac = gmac_dpll_params_2000mhz,
 308 };
 309
 310 struct pmic_data palmas = {
 311         .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
 312         .step = 10000, /* 10 mV represented in uV */
 313         /*
 314          * Offset codes 1-6 all give the base voltage in Palmas
 315          * Offset code 0 switches OFF the SMPS
 316          */
 317         .start_code = 6,
 318         .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
 319         .pmic_bus_init  = sri2c_init,
 320         .pmic_write     = omap_vc_bypass_send_value,
 321 };
 322
 323 /* The TPS659038 and TPS65917 are software-compatible, use common struct */
 324 struct pmic_data tps659038 = {
 325         .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
 326         .step = 10000, /* 10 mV represented in uV */
 327         /*
 328          * Offset codes 1-6 all give the base voltage in Palmas
 329          * Offset code 0 switches OFF the SMPS
 330          */
 331         .start_code = 6,
 332         .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
 333         .pmic_bus_init  = gpi2c_init,
 334         .pmic_write     = palmas_i2c_write_u8,
 335 };
 336
 337 struct vcores_data omap5430_volts = {
 338         .mpu.value = VDD_MPU,
 339         .mpu.addr = SMPS_REG_ADDR_12_MPU,
 340         .mpu.pmic = &palmas,
 341
 342         .core.value = VDD_CORE,
 343         .core.addr = SMPS_REG_ADDR_8_CORE,
 344         .core.pmic = &palmas,
 345
 346         .mm.value = VDD_MM,
 347         .mm.addr = SMPS_REG_ADDR_45_IVA,
 348         .mm.pmic = &palmas,
 349 };
 350
 351 struct vcores_data omap5430_volts_es2 = {
 352         .mpu.value = VDD_MPU_ES2,
 353         .mpu.addr = SMPS_REG_ADDR_12_MPU,
 354         .mpu.pmic = &palmas,
 355         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 356
 357         .core.value = VDD_CORE_ES2,
 358         .core.addr = SMPS_REG_ADDR_8_CORE,
 359         .core.pmic = &palmas,
 360
 361         .mm.value = VDD_MM_ES2,
 362         .mm.addr = SMPS_REG_ADDR_45_IVA,
 363         .mm.pmic = &palmas,
 364         .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
 365 };
 366
 367 struct vcores_data dra752_volts = {
 368         .mpu.value      = VDD_MPU_DRA752,
 369         .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU_NOM,
 370         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 371         .mpu.addr       = TPS659038_REG_ADDR_SMPS12,
 372         .mpu.pmic       = &tps659038,
 373         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 374
 375         .eve.value      = VDD_EVE_DRA752,
 376         .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 377         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 378         .eve.addr       = TPS659038_REG_ADDR_SMPS45,
 379         .eve.pmic       = &tps659038,
 380
 381         .gpu.value      = VDD_GPU_DRA752,
 382         .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU_NOM,
 383         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 384         .gpu.addr       = TPS659038_REG_ADDR_SMPS6,
 385         .gpu.pmic       = &tps659038,
 386
 387         .core.value     = VDD_CORE_DRA752,
 388         .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
 389         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 390         .core.addr      = TPS659038_REG_ADDR_SMPS7,
 391         .core.pmic      = &tps659038,
 392
 393         .iva.value      = VDD_IVA_DRA752,
 394         .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA_NOM,
 395         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 396         .iva.addr       = TPS659038_REG_ADDR_SMPS8,
 397         .iva.pmic       = &tps659038,
 398 };
 399
 400 struct vcores_data dra722_volts = {
 401         .mpu.value      = VDD_MPU_DRA72x,
 402         .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU_NOM,
 403         .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 404         .mpu.addr       = TPS65917_REG_ADDR_SMPS1,
 405         .mpu.pmic       = &tps659038,
 406         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 407
 408         .core.value     = VDD_CORE_DRA72x,
 409         .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
 410         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 411         .core.addr      = TPS65917_REG_ADDR_SMPS2,
 412         .core.pmic      = &tps659038,
 413
 414         /*
 415          * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
 416          * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
 417          */
 418         .gpu.value      = VDD_GPU_DRA72x,
 419         .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU_NOM,
 420         .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 421         .gpu.addr       = TPS65917_REG_ADDR_SMPS3,
 422         .gpu.pmic       = &tps659038,
 423
 424         .eve.value      = VDD_EVE_DRA72x,
 425         .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 426         .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 427         .eve.addr       = TPS65917_REG_ADDR_SMPS3,
 428         .eve.pmic       = &tps659038,
 429
 430         .iva.value      = VDD_IVA_DRA72x,
 431         .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA_NOM,
 432         .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 433         .iva.addr       = TPS65917_REG_ADDR_SMPS3,
 434         .iva.pmic       = &tps659038,
 435 };
 436
 437 /*
 438  * Enable essential clock domains, modules and
 439  * do some additional special settings needed
 440  */
 441 void enable_basic_clocks(void)
 442 {
 443         u32 const clk_domains_essential[] = {
 444                 (*prcm)->cm_l4per_clkstctrl,
 445                 (*prcm)->cm_l3init_clkstctrl,
 446                 (*prcm)->cm_memif_clkstctrl,
 447                 (*prcm)->cm_l4cfg_clkstctrl,
 448 #ifdef CONFIG_DRIVER_TI_CPSW
 449                 (*prcm)->cm_gmac_clkstctrl,
 450 #endif
 451                 0
 452         };
 453
 454         u32 const clk_modules_hw_auto_essential[] = {
 455                 (*prcm)->cm_l3_gpmc_clkctrl,
 456                 (*prcm)->cm_memif_emif_1_clkctrl,
 457                 (*prcm)->cm_memif_emif_2_clkctrl,
 458                 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
 459                 (*prcm)->cm_wkup_gpio1_clkctrl,
 460                 (*prcm)->cm_l4per_gpio2_clkctrl,
 461                 (*prcm)->cm_l4per_gpio3_clkctrl,
 462                 (*prcm)->cm_l4per_gpio4_clkctrl,
 463                 (*prcm)->cm_l4per_gpio5_clkctrl,
 464                 (*prcm)->cm_l4per_gpio6_clkctrl,
 465                 (*prcm)->cm_l4per_gpio7_clkctrl,
 466                 (*prcm)->cm_l4per_gpio8_clkctrl,
 467                 0
 468         };
 469
 470         u32 const clk_modules_explicit_en_essential[] = {
 471                 (*prcm)->cm_wkup_gptimer1_clkctrl,
 472                 (*prcm)->cm_l3init_hsmmc1_clkctrl,
 473                 (*prcm)->cm_l3init_hsmmc2_clkctrl,
 474                 (*prcm)->cm_l4per_gptimer2_clkctrl,
 475                 (*prcm)->cm_wkup_wdtimer2_clkctrl,
 476                 (*prcm)->cm_l4per_uart3_clkctrl,
 477                 (*prcm)->cm_l4per_i2c1_clkctrl,
 478 #ifdef CONFIG_DRIVER_TI_CPSW
 479                 (*prcm)->cm_gmac_gmac_clkctrl,
 480 #endif
 481
 482 #ifdef CONFIG_TI_QSPI
 483                 (*prcm)->cm_l4per_qspi_clkctrl,
 484 #endif
 485                 0
 486         };
 487
 488         /* Enable optional additional functional clock for GPIO4 */
 489         setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
 490                         GPIO4_CLKCTRL_OPTFCLKEN_MASK);
 491
 492         /* Enable 96 MHz clock for MMC1 & MMC2 */
 493         setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 494                         HSMMC_CLKCTRL_CLKSEL_MASK);
 495         setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 496                         HSMMC_CLKCTRL_CLKSEL_MASK);
 497
 498         /* Set the correct clock dividers for mmc */
 499         setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 500                         HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 501         setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 502                         HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 503
 504         /* Select 32KHz clock as the source of GPTIMER1 */
 505         setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
 506                         GPTIMER1_CLKCTRL_CLKSEL_MASK);
 507
 508         do_enable_clocks(clk_domains_essential,
 509                          clk_modules_hw_auto_essential,
 510                          clk_modules_explicit_en_essential,
 511                          1);
 512
 513 #ifdef CONFIG_TI_QSPI
 514         setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
 515 #endif
 516
 517         /* Enable SCRM OPT clocks for PER and CORE dpll */
 518         setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 519                         OPTFCLKEN_SCRM_PER_MASK);
 520         setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 521                         OPTFCLKEN_SCRM_CORE_MASK);
 522 }
 523
 524 void enable_basic_uboot_clocks(void)
 525 {
 526         u32 const clk_domains_essential[] = {
 527 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 528                 (*prcm)->cm_ipu_clkstctrl,
 529 #endif
 530                 0
 531         };
 532
 533         u32 const clk_modules_hw_auto_essential[] = {
 534                 (*prcm)->cm_l3init_hsusbtll_clkctrl,
 535                 0
 536         };
 537
 538         u32 const clk_modules_explicit_en_essential[] = {
 539                 (*prcm)->cm_l4per_mcspi1_clkctrl,
 540                 (*prcm)->cm_l4per_i2c2_clkctrl,
 541                 (*prcm)->cm_l4per_i2c3_clkctrl,
 542                 (*prcm)->cm_l4per_i2c4_clkctrl,
 543 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 544                 (*prcm)->cm_ipu_i2c5_clkctrl,
 545 #else
 546                 (*prcm)->cm_l4per_i2c5_clkctrl,
 547 #endif
 548                 (*prcm)->cm_l3init_hsusbhost_clkctrl,
 549                 (*prcm)->cm_l3init_fsusb_clkctrl,
 550                 0
 551         };
 552         do_enable_clocks(clk_domains_essential,
 553                          clk_modules_hw_auto_essential,
 554                          clk_modules_explicit_en_essential,
 555                          1);
 556 }
 557
 558 #ifdef CONFIG_TI_EDMA3
 559 void enable_edma3_clocks(void)
 560 {
 561         u32 const clk_domains_edma3[] = {
 562                 0
 563         };
 564
 565         u32 const clk_modules_hw_auto_edma3[] = {
 566                 (*prcm)->cm_l3main1_tptc1_clkctrl,
 567                 (*prcm)->cm_l3main1_tptc2_clkctrl,
 568                 0
 569         };
 570
 571         u32 const clk_modules_explicit_en_edma3[] = {
 572                 0
 573         };
 574
 575         do_enable_clocks(clk_domains_edma3,
 576                          clk_modules_hw_auto_edma3,
 577                          clk_modules_explicit_en_edma3,
 578                          1);
 579 }
 580
 581 void disable_edma3_clocks(void)
 582 {
 583         u32 const clk_domains_edma3[] = {
 584                 0
 585         };
 586
 587         u32 const clk_modules_disable_edma3[] = {
 588                 (*prcm)->cm_l3main1_tptc1_clkctrl,
 589                 (*prcm)->cm_l3main1_tptc2_clkctrl,
 590                 0
 591         };
 592
 593         do_disable_clocks(clk_domains_edma3,
 594                           clk_modules_disable_edma3,
 595                           1);
 596 }
 597 #endif
 598
 599 #ifdef CONFIG_USB_DWC3
 600 void enable_usb_clocks(int index)
 601 {
 602         u32 cm_l3init_usb_otg_ss_clkctrl = 0;
 603
 604         if (index == 0) {
 605                 cm_l3init_usb_otg_ss_clkctrl =
 606                         (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
 607                 /* Enable 960 MHz clock for dwc3 */
 608                 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 609                              OPTFCLKEN_REFCLK960M);
 610
 611                 /* Enable 32 KHz clock for dwc3 */
 612                 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
 613                              USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
 614         } else if (index == 1) {
 615                 cm_l3init_usb_otg_ss_clkctrl =
 616                         (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
 617                 /* Enable 960 MHz clock for dwc3 */
 618                 setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
 619                              OPTFCLKEN_REFCLK960M);
 620
 621                 /* Enable 32 KHz clock for dwc3 */
 622                 setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
 623                              USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
 624
 625                 /* Enable 60 MHz clock for USB2PHY2 */
 626                 setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
 627                              L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
 628         }
 629
 630         u32 const clk_domains_usb[] = {
 631                 0
 632         };
 633
 634         u32 const clk_modules_hw_auto_usb[] = {
 635                 (*prcm)->cm_l3init_ocp2scp1_clkctrl,
 636                 cm_l3init_usb_otg_ss_clkctrl,
 637                 0
 638         };
 639
 640         u32 const clk_modules_explicit_en_usb[] = {
 641                 0
 642         };
 643
 644         do_enable_clocks(clk_domains_usb,
 645                          clk_modules_hw_auto_usb,
 646                          clk_modules_explicit_en_usb,
 647                          1);
 648 }
 649
 650 void disable_usb_clocks(int index)
 651 {
 652         u32 cm_l3init_usb_otg_ss_clkctrl = 0;
 653
 654         if (index == 0) {
 655                 cm_l3init_usb_otg_ss_clkctrl =
 656                         (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
 657                 /* Disable 960 MHz clock for dwc3 */
 658                 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 659                              OPTFCLKEN_REFCLK960M);
 660
 661                 /* Disable 32 KHz clock for dwc3 */
 662                 clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
 663                              USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
 664         } else if (index == 1) {
 665                 cm_l3init_usb_otg_ss_clkctrl =
 666                         (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
 667                 /* Disable 960 MHz clock for dwc3 */
 668                 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
 669                              OPTFCLKEN_REFCLK960M);
 670
 671                 /* Disable 32 KHz clock for dwc3 */
 672                 clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
 673                              USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
 674
 675                 /* Disable 60 MHz clock for USB2PHY2 */
 676                 clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
 677                              L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
 678         }
 679
 680         u32 const clk_domains_usb[] = {
 681                 0
 682         };
 683
 684         u32 const clk_modules_disable[] = {
 685                 (*prcm)->cm_l3init_ocp2scp1_clkctrl,
 686                 cm_l3init_usb_otg_ss_clkctrl,
 687                 0
 688         };
 689
 690         do_disable_clocks(clk_domains_usb,
 691                           clk_modules_disable,
 692                           1);
 693 }
 694 #endif
 695
 696 const struct ctrl_ioregs ioregs_omap5430 = {
 697         .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
 698         .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
 699         .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
 700         .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
 701         .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
 702 };
 703
 704 const struct ctrl_ioregs ioregs_omap5432_es1 = {
 705         .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
 706         .ctrl_lpddr2ch = 0x0,
 707         .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
 708         .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
 709         .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
 710         .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
 711         .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 712         .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 713 };
 714
 715 const struct ctrl_ioregs ioregs_omap5432_es2 = {
 716         .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
 717         .ctrl_lpddr2ch = 0x0,
 718         .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
 719         .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
 720         .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
 721         .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
 722         .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 723         .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 724 };
 725
 726 const struct ctrl_ioregs ioregs_dra7xx_es1 = {
 727         .ctrl_ddrch = 0x40404040,
 728         .ctrl_lpddr2ch = 0x40404040,
 729         .ctrl_ddr3ch = 0x80808080,
 730         .ctrl_ddrio_0 = 0x00094A40,
 731         .ctrl_ddrio_1 = 0x04A52000,
 732         .ctrl_ddrio_2 = 0x84210000,
 733         .ctrl_emif_sdram_config_ext = 0x0001C1A7,
 734         .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
 735         .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 736 };
 737
 738 const struct ctrl_ioregs ioregs_dra72x_es1 = {
 739         .ctrl_ddrch = 0x40404040,
 740         .ctrl_lpddr2ch = 0x40404040,
 741         .ctrl_ddr3ch = 0x60606080,
 742         .ctrl_ddrio_0 = 0x00094A40,
 743         .ctrl_ddrio_1 = 0x04A52000,
 744         .ctrl_ddrio_2 = 0x84210000,
 745         .ctrl_emif_sdram_config_ext = 0x0001C1A7,
 746         .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
 747         .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 748 };
 749
 750 const struct ctrl_ioregs ioregs_dra72x_es2 = {
 751         .ctrl_ddrch = 0x40404040,
 752         .ctrl_lpddr2ch = 0x40404040,
 753         .ctrl_ddr3ch = 0x60606060,
 754         .ctrl_ddrio_0 = 0x00094A40,
 755         .ctrl_ddrio_1 = 0x00000000,
 756         .ctrl_ddrio_2 = 0x00000000,
 757         .ctrl_emif_sdram_config_ext = 0x0001C1A7,
 758         .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
 759         .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 760 };
 761
 762 void __weak hw_data_init(void)
 763 {
 764         u32 omap_rev = omap_revision();
 765
 766         switch (omap_rev) {
 767
 768         case OMAP5430_ES1_0:
 769         case OMAP5432_ES1_0:
 770         *prcm = &omap5_es1_prcm;
 771         *dplls_data = &omap5_dplls_es1;
 772         *omap_vcores = &omap5430_volts;
 773         *ctrl = &omap5_ctrl;
 774         break;
 775
 776         case OMAP5430_ES2_0:
 777         case OMAP5432_ES2_0:
 778         *prcm = &omap5_es2_prcm;
 779         *dplls_data = &omap5_dplls_es2;
 780         *omap_vcores = &omap5430_volts_es2;
 781         *ctrl = &omap5_ctrl;
 782         break;
 783
 784         case DRA752_ES1_0:
 785         case DRA752_ES1_1:
 786         case DRA752_ES2_0:
 787         *prcm = &dra7xx_prcm;
 788         *dplls_data = &dra7xx_dplls;
 789         *omap_vcores = &dra752_volts;
 790         *ctrl = &dra7xx_ctrl;
 791         break;
 792
 793         case DRA722_ES1_0:
 794         case DRA722_ES2_0:
 795         *prcm = &dra7xx_prcm;
 796         *dplls_data = &dra72x_dplls;
 797         *omap_vcores = &dra722_volts;
 798         *ctrl = &dra7xx_ctrl;
 799         break;
 800
 801         default:
 802                 printf("\n INVALID OMAP REVISION ");
 803         }
 804 }
 805
 806 void get_ioregs(const struct ctrl_ioregs **regs)
 807 {
 808         u32 omap_rev = omap_revision();
 809
 810         switch (omap_rev) {
 811         case OMAP5430_ES1_0:
 812         case OMAP5430_ES2_0:
 813                 *regs = &ioregs_omap5430;
 814                 break;
 815         case OMAP5432_ES1_0:
 816                 *regs = &ioregs_omap5432_es1;
 817                 break;
 818         case OMAP5432_ES2_0:
 819                 *regs = &ioregs_omap5432_es2;
 820                 break;
 821         case DRA752_ES1_0:
 822         case DRA752_ES1_1:
 823         case DRA752_ES2_0:
 824                 *regs = &ioregs_dra7xx_es1;
 825                 break;
 826         case DRA722_ES1_0:
 827                 *regs = &ioregs_dra72x_es1;
 828                 break;
 829         case DRA722_ES2_0:
 830                 *regs = &ioregs_dra72x_es2;
 831                 break;
 832
 833         default:
 834                 printf("\n INVALID OMAP REVISION ");
 835         }
 836 }