arch/arm/cpu/armv7/omap5/hw_data.c

   1 /*
   2  *
   3  * HW data initialization for OMAP5
   4  *
   5  * (C) Copyright 2013
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Sricharan R <r.sricharan@ti.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12 #include <common.h>
  13 #include <palmas.h>
  14 #include <asm/arch/omap.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/omap_gpio.h>
  19 #include <asm/io.h>
  20 #include <asm/emif.h>
  21
  22 struct prcm_regs const **prcm =
  23                         (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
  24 struct dplls const **dplls_data =
  25                         (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
  26 struct vcores_data const **omap_vcores =
  27                 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
  28 struct omap_sys_ctrl_regs const **ctrl =
  29         (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
  30
  31 /* OPP HIGH FREQUENCY for ES2.0 */
  32 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
  33         {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  34         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  35         {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
  36         {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  37         {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  38         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  39         {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  40 };
  41
  42 /* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
  43 static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
  44         {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  45         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  46         {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 16.8 MHz */
  47         {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 19.2 MHz */
  48         {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  49         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  50         {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}       /* 38.4 MHz */
  51 };
  52
  53 /* OPP NOM FREQUENCY for ES1.0 */
  54 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
  55         {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  56         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  57         {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 16.8 MHz */
  58         {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  59         {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  60         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  61         {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  62 };
  63
  64 /* OPP LOW FREQUENCY for ES1.0 */
  65 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
  66         {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  67         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  68         {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 16.8 MHz */
  69         {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  70         {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  71         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  72         {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  73 };
  74
  75 /* OPP LOW FREQUENCY for ES2.0 */
  76 static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
  77         {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
  78         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  79         {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
  80         {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
  81         {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  82         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  83         {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  84 };
  85
  86 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
  87         {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
  88         {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz   */
  89         {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
  90         {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  91         {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 26 MHz   */
  92         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  93         {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 38.4 MHz */
  94 };
  95
  96 static const struct dpll_params
  97                         core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
  98         {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 12 MHz   */
  99         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 100         {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 16.8 MHz */
 101         {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 19.2 MHz */
 102         {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 26 MHz   */
 103         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 104         {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}               /* 38.4 MHz */
 105 };
 106
 107 static const struct dpll_params
 108                         core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
 109         {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 12 MHz   */
 110         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 111         {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 16.8 MHz */
 112         {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 19.2 MHz */
 113         {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 26 MHz   */
 114         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 115         {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}                /* 38.4 MHz */
 116 };
 117
 118 static const struct dpll_params
 119                 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
 120         {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 12 MHz   */
 121         {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 20 MHz   */
 122         {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 16.8 MHz */
 123         {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 19.2 MHz */
 124         {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 26 MHz   */
 125         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 126         {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 38.4 MHz */
 127 };
 128
 129 static const struct dpll_params
 130                         core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
 131         {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 12 MHz   */
 132         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 133         {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 16.8 MHz */
 134         {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 19.2 MHz */
 135         {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 26 MHz   */
 136         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 137         {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}            /* 38.4 MHz */
 138 };
 139
 140 static const struct dpll_params
 141                         core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
 142         {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 12 MHz   */
 143         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 144         {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 16.8 MHz */
 145         {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 19.2 MHz */
 146         {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 26 MHz   */
 147         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 148         {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}             /* 38.4 MHz */
 149 };
 150
 151 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
 152         {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},             /* 12 MHz   */
 153         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 154         {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},            /* 16.8 MHz */
 155         {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},             /* 19.2 MHz */
 156         {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},           /* 26 MHz   */
 157         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 158         {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}              /* 38.4 MHz */
 159 };
 160
 161 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 162         {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},             /* 12 MHz   */
 163         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 164         {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},            /* 16.8 MHz */
 165         {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},             /* 19.2 MHz */
 166         {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},           /* 26 MHz   */
 167         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 168         {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}              /* 38.4 MHz */
 169 };
 170
 171 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
 172         {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 12 MHz   */
 173         {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 20 MHz   */
 174         {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 16.8 MHz */
 175         {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 19.2 MHz */
 176         {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},           /* 26 MHz   */
 177         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 178         {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 38.4 MHz */
 179 };
 180
 181 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
 182         {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 183         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 184         {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
 185         {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 186         {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 187         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 188         {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}           /* 38.4 MHz */
 189 };
 190
 191 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
 192         {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 193         {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz */
 194         {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
 195         {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 196         {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 197         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 198         {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 38.4 MHz */
 199 };
 200
 201 /* ABE M & N values with sys_clk as source */
 202 static const struct dpll_params
 203                 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
 204         {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
 205         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 206         {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
 207         {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 19.2 MHz */
 208         {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 26 MHz   */
 209         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 210         {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}          /* 38.4 MHz */
 211 };
 212
 213 /* ABE M & N values with 32K clock as source */
 214 static const struct dpll_params abe_dpll_params_32k_196608khz = {
 215         750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
 216 };
 217
 218 /* ABE M & N values with sysclk2(22.5792 MHz) as input */
 219 static const struct dpll_params
 220                 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
 221         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 222         {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
 223         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 16.8 MHz */
 224         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
 225         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
 226         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 227         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
 228 };
 229
 230 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
 231         {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
 232         {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 20 MHz   */
 233         {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
 234         {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
 235         {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
 236         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 237         {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
 238 };
 239
 240 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
 241         {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 12 MHz   */
 242         {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
 243         {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
 244         {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 245         {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 246         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 247         {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 38.4 MHz */
 248 };
 249
 250 static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
 251         {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},         /* 12 MHz   */
 252         {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},         /* 20 MHz   */
 253         {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},         /* 16.8 MHz */
 254         {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},        /* 19.2 MHz */
 255         {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},        /* 26 MHz   */
 256         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 257         {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},        /* 38.4 MHz */
 258 };
 259
 260 struct dplls omap5_dplls_es1 = {
 261         .mpu = mpu_dpll_params_800mhz,
 262         .core = core_dpll_params_2128mhz_ddr532,
 263         .per = per_dpll_params_768mhz,
 264         .iva = iva_dpll_params_2330mhz,
 265 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 266         .abe = abe_dpll_params_sysclk_196608khz,
 267 #else
 268         .abe = &abe_dpll_params_32k_196608khz,
 269 #endif
 270         .usb = usb_dpll_params_1920mhz,
 271         .ddr = NULL
 272 };
 273
 274 struct dplls omap5_dplls_es2 = {
 275         .mpu = mpu_dpll_params_1100mhz,
 276         .core = core_dpll_params_2128mhz_ddr532_es2,
 277         .per = per_dpll_params_768mhz_es2,
 278         .iva = iva_dpll_params_2330mhz,
 279 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 280         .abe = abe_dpll_params_sysclk_196608khz,
 281 #else
 282         .abe = &abe_dpll_params_32k_196608khz,
 283 #endif
 284         .usb = usb_dpll_params_1920mhz,
 285         .ddr = NULL
 286 };
 287
 288 struct dplls dra7xx_dplls = {
 289         .mpu = mpu_dpll_params_1ghz,
 290         .core = core_dpll_params_2128mhz_dra7xx,
 291         .per = per_dpll_params_768mhz_dra7xx,
 292         .abe = abe_dpll_params_sysclk2_361267khz,
 293         .iva = iva_dpll_params_2330mhz_dra7xx,
 294         .usb = usb_dpll_params_1920mhz,
 295         .ddr = ddr_dpll_params_2128mhz,
 296         .gmac = gmac_dpll_params_2000mhz,
 297 };
 298
 299 struct pmic_data palmas = {
 300         .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
 301         .step = 10000, /* 10 mV represented in uV */
 302         /*
 303          * Offset codes 1-6 all give the base voltage in Palmas
 304          * Offset code 0 switches OFF the SMPS
 305          */
 306         .start_code = 6,
 307         .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
 308         .pmic_bus_init  = sri2c_init,
 309         .pmic_write     = omap_vc_bypass_send_value,
 310 };
 311
 312 struct pmic_data tps659038 = {
 313         .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
 314         .step = 10000, /* 10 mV represented in uV */
 315         /*
 316          * Offset codes 1-6 all give the base voltage in Palmas
 317          * Offset code 0 switches OFF the SMPS
 318          */
 319         .start_code = 6,
 320         .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
 321         .pmic_bus_init  = gpi2c_init,
 322         .pmic_write     = palmas_i2c_write_u8,
 323 };
 324
 325 struct vcores_data omap5430_volts = {
 326         .mpu.value = VDD_MPU,
 327         .mpu.addr = SMPS_REG_ADDR_12_MPU,
 328         .mpu.pmic = &palmas,
 329
 330         .core.value = VDD_CORE,
 331         .core.addr = SMPS_REG_ADDR_8_CORE,
 332         .core.pmic = &palmas,
 333
 334         .mm.value = VDD_MM,
 335         .mm.addr = SMPS_REG_ADDR_45_IVA,
 336         .mm.pmic = &palmas,
 337 };
 338
 339 struct vcores_data omap5430_volts_es2 = {
 340         .mpu.value = VDD_MPU_ES2,
 341         .mpu.addr = SMPS_REG_ADDR_12_MPU,
 342         .mpu.pmic = &palmas,
 343
 344         .core.value = VDD_CORE_ES2,
 345         .core.addr = SMPS_REG_ADDR_8_CORE,
 346         .core.pmic = &palmas,
 347
 348         .mm.value = VDD_MM_ES2,
 349         .mm.addr = SMPS_REG_ADDR_45_IVA,
 350         .mm.pmic = &palmas,
 351 };
 352
 353 struct vcores_data dra752_volts = {
 354         .mpu.value      = VDD_MPU_DRA752,
 355         .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU_NOM,
 356         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 357         .mpu.addr       = TPS659038_REG_ADDR_SMPS12_MPU,
 358         .mpu.pmic       = &tps659038,
 359
 360         .eve.value      = VDD_EVE_DRA752,
 361         .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 362         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 363         .eve.addr       = TPS659038_REG_ADDR_SMPS45_EVE,
 364         .eve.pmic       = &tps659038,
 365
 366         .gpu.value      = VDD_GPU_DRA752,
 367         .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU_NOM,
 368         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 369         .gpu.addr       = TPS659038_REG_ADDR_SMPS6_GPU,
 370         .gpu.pmic       = &tps659038,
 371
 372         .core.value     = VDD_CORE_DRA752,
 373         .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
 374         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 375         .core.addr      = TPS659038_REG_ADDR_SMPS7_CORE,
 376         .core.pmic      = &tps659038,
 377
 378         .iva.value      = VDD_IVA_DRA752,
 379         .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA_NOM,
 380         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 381         .iva.addr       = TPS659038_REG_ADDR_SMPS8_IVA,
 382         .iva.pmic       = &tps659038,
 383 };
 384
 385 /*
 386  * Enable essential clock domains, modules and
 387  * do some additional special settings needed
 388  */
 389 void enable_basic_clocks(void)
 390 {
 391         u32 const clk_domains_essential[] = {
 392                 (*prcm)->cm_l4per_clkstctrl,
 393                 (*prcm)->cm_l3init_clkstctrl,
 394                 (*prcm)->cm_memif_clkstctrl,
 395                 (*prcm)->cm_l4cfg_clkstctrl,
 396 #ifdef CONFIG_DRIVER_TI_CPSW
 397                 (*prcm)->cm_gmac_clkstctrl,
 398 #endif
 399                 0
 400         };
 401
 402         u32 const clk_modules_hw_auto_essential[] = {
 403                 (*prcm)->cm_l3_gpmc_clkctrl,
 404                 (*prcm)->cm_memif_emif_1_clkctrl,
 405                 (*prcm)->cm_memif_emif_2_clkctrl,
 406                 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
 407                 (*prcm)->cm_wkup_gpio1_clkctrl,
 408                 (*prcm)->cm_l4per_gpio2_clkctrl,
 409                 (*prcm)->cm_l4per_gpio3_clkctrl,
 410                 (*prcm)->cm_l4per_gpio4_clkctrl,
 411                 (*prcm)->cm_l4per_gpio5_clkctrl,
 412                 (*prcm)->cm_l4per_gpio6_clkctrl,
 413                 (*prcm)->cm_l4per_gpio7_clkctrl,
 414                 (*prcm)->cm_l4per_gpio8_clkctrl,
 415                 0
 416         };
 417
 418         u32 const clk_modules_explicit_en_essential[] = {
 419                 (*prcm)->cm_wkup_gptimer1_clkctrl,
 420                 (*prcm)->cm_l3init_hsmmc1_clkctrl,
 421                 (*prcm)->cm_l3init_hsmmc2_clkctrl,
 422                 (*prcm)->cm_l4per_gptimer2_clkctrl,
 423                 (*prcm)->cm_wkup_wdtimer2_clkctrl,
 424                 (*prcm)->cm_l4per_uart3_clkctrl,
 425                 (*prcm)->cm_l4per_i2c1_clkctrl,
 426 #ifdef CONFIG_DRIVER_TI_CPSW
 427                 (*prcm)->cm_gmac_gmac_clkctrl,
 428 #endif
 429
 430 #ifdef CONFIG_TI_QSPI
 431                 (*prcm)->cm_l4per_qspi_clkctrl,
 432 #endif
 433                 0
 434         };
 435
 436         /* Enable optional additional functional clock for GPIO4 */
 437         setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
 438                         GPIO4_CLKCTRL_OPTFCLKEN_MASK);
 439
 440         /* Enable 96 MHz clock for MMC1 & MMC2 */
 441         setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 442                         HSMMC_CLKCTRL_CLKSEL_MASK);
 443         setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 444                         HSMMC_CLKCTRL_CLKSEL_MASK);
 445
 446         /* Set the correct clock dividers for mmc */
 447         setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 448                         HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 449         setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 450                         HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 451
 452         /* Select 32KHz clock as the source of GPTIMER1 */
 453         setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
 454                         GPTIMER1_CLKCTRL_CLKSEL_MASK);
 455
 456         do_enable_clocks(clk_domains_essential,
 457                          clk_modules_hw_auto_essential,
 458                          clk_modules_explicit_en_essential,
 459                          1);
 460
 461 #ifdef CONFIG_TI_QSPI
 462         setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
 463 #endif
 464
 465         /* Enable SCRM OPT clocks for PER and CORE dpll */
 466         setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 467                         OPTFCLKEN_SCRM_PER_MASK);
 468         setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 469                         OPTFCLKEN_SCRM_CORE_MASK);
 470 }
 471
 472 void enable_basic_uboot_clocks(void)
 473 {
 474         u32 const clk_domains_essential[] = {
 475                 0
 476         };
 477
 478         u32 const clk_modules_hw_auto_essential[] = {
 479                 (*prcm)->cm_l3init_hsusbtll_clkctrl,
 480                 0
 481         };
 482
 483         u32 const clk_modules_explicit_en_essential[] = {
 484                 (*prcm)->cm_l4per_mcspi1_clkctrl,
 485                 (*prcm)->cm_l4per_i2c2_clkctrl,
 486                 (*prcm)->cm_l4per_i2c3_clkctrl,
 487                 (*prcm)->cm_l4per_i2c4_clkctrl,
 488                 (*prcm)->cm_l4per_i2c5_clkctrl,
 489                 (*prcm)->cm_l3init_hsusbhost_clkctrl,
 490                 (*prcm)->cm_l3init_fsusb_clkctrl,
 491                 0
 492         };
 493         do_enable_clocks(clk_domains_essential,
 494                          clk_modules_hw_auto_essential,
 495                          clk_modules_explicit_en_essential,
 496                          1);
 497 }
 498
 499 /*
 500  * Enable non-essential clock domains, modules and
 501  * do some additional special settings needed
 502  */
 503 void enable_non_essential_clocks(void)
 504 {
 505         u32 const clk_domains_non_essential[] = {
 506                 (*prcm)->cm_mpu_m3_clkstctrl,
 507                 (*prcm)->cm_ivahd_clkstctrl,
 508                 (*prcm)->cm_dsp_clkstctrl,
 509                 (*prcm)->cm_dss_clkstctrl,
 510                 (*prcm)->cm_sgx_clkstctrl,
 511                 (*prcm)->cm1_abe_clkstctrl,
 512                 (*prcm)->cm_c2c_clkstctrl,
 513                 (*prcm)->cm_cam_clkstctrl,
 514                 (*prcm)->cm_dss_clkstctrl,
 515                 (*prcm)->cm_sdma_clkstctrl,
 516                 0
 517         };
 518
 519         u32 const clk_modules_hw_auto_non_essential[] = {
 520                 (*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
 521                 (*prcm)->cm_ivahd_ivahd_clkctrl,
 522                 (*prcm)->cm_ivahd_sl2_clkctrl,
 523                 (*prcm)->cm_dsp_dsp_clkctrl,
 524                 (*prcm)->cm_l3instr_l3_3_clkctrl,
 525                 (*prcm)->cm_l3instr_l3_instr_clkctrl,
 526                 (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
 527                 (*prcm)->cm_l3init_hsi_clkctrl,
 528                 (*prcm)->cm_l4per_hdq1w_clkctrl,
 529                 0
 530         };
 531
 532         u32 const clk_modules_explicit_en_non_essential[] = {
 533                 (*prcm)->cm1_abe_aess_clkctrl,
 534                 (*prcm)->cm1_abe_pdm_clkctrl,
 535                 (*prcm)->cm1_abe_dmic_clkctrl,
 536                 (*prcm)->cm1_abe_mcasp_clkctrl,
 537                 (*prcm)->cm1_abe_mcbsp1_clkctrl,
 538                 (*prcm)->cm1_abe_mcbsp2_clkctrl,
 539                 (*prcm)->cm1_abe_mcbsp3_clkctrl,
 540                 (*prcm)->cm1_abe_slimbus_clkctrl,
 541                 (*prcm)->cm1_abe_timer5_clkctrl,
 542                 (*prcm)->cm1_abe_timer6_clkctrl,
 543                 (*prcm)->cm1_abe_timer7_clkctrl,
 544                 (*prcm)->cm1_abe_timer8_clkctrl,
 545                 (*prcm)->cm1_abe_wdt3_clkctrl,
 546                 (*prcm)->cm_l4per_gptimer9_clkctrl,
 547                 (*prcm)->cm_l4per_gptimer10_clkctrl,
 548                 (*prcm)->cm_l4per_gptimer11_clkctrl,
 549                 (*prcm)->cm_l4per_gptimer3_clkctrl,
 550                 (*prcm)->cm_l4per_gptimer4_clkctrl,
 551                 (*prcm)->cm_l4per_mcspi2_clkctrl,
 552                 (*prcm)->cm_l4per_mcspi3_clkctrl,
 553                 (*prcm)->cm_l4per_mcspi4_clkctrl,
 554                 (*prcm)->cm_l4per_mmcsd3_clkctrl,
 555                 (*prcm)->cm_l4per_mmcsd4_clkctrl,
 556                 (*prcm)->cm_l4per_mmcsd5_clkctrl,
 557                 (*prcm)->cm_l4per_uart1_clkctrl,
 558                 (*prcm)->cm_l4per_uart2_clkctrl,
 559                 (*prcm)->cm_l4per_uart4_clkctrl,
 560                 (*prcm)->cm_wkup_keyboard_clkctrl,
 561                 (*prcm)->cm_wkup_wdtimer2_clkctrl,
 562                 (*prcm)->cm_cam_iss_clkctrl,
 563                 (*prcm)->cm_cam_fdif_clkctrl,
 564                 (*prcm)->cm_dss_dss_clkctrl,
 565                 (*prcm)->cm_sgx_sgx_clkctrl,
 566                 0
 567         };
 568
 569         /* Enable optional functional clock for ISS */
 570         setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
 571
 572         /* Enable all optional functional clocks of DSS */
 573         setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
 574
 575         do_enable_clocks(clk_domains_non_essential,
 576                          clk_modules_hw_auto_non_essential,
 577                          clk_modules_explicit_en_non_essential,
 578                          0);
 579
 580         /* Put camera module in no sleep mode */
 581         clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
 582                         MODULE_CLKCTRL_MODULEMODE_MASK,
 583                         CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
 584                         MODULE_CLKCTRL_MODULEMODE_SHIFT);
 585 }
 586
 587 const struct ctrl_ioregs ioregs_omap5430 = {
 588         .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
 589         .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
 590         .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
 591         .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
 592         .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
 593 };
 594
 595 const struct ctrl_ioregs ioregs_omap5432_es1 = {
 596         .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
 597         .ctrl_lpddr2ch = 0x0,
 598         .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
 599         .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
 600         .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
 601         .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
 602         .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 603 };
 604
 605 const struct ctrl_ioregs ioregs_omap5432_es2 = {
 606         .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
 607         .ctrl_lpddr2ch = 0x0,
 608         .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
 609         .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
 610         .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
 611         .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
 612         .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 613 };
 614
 615 const struct ctrl_ioregs ioregs_dra7xx_es1 = {
 616         .ctrl_ddrch = 0x40404040,
 617         .ctrl_lpddr2ch = 0x40404040,
 618         .ctrl_ddr3ch = 0x80808080,
 619         .ctrl_ddrio_0 = 0xbae8c631,
 620         .ctrl_ddrio_1 = 0xb46318d8,
 621         .ctrl_ddrio_2 = 0x84210000,
 622         .ctrl_emif_sdram_config_ext = 0xb2c00000,
 623         .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 624 };
 625
 626 void hw_data_init(void)
 627 {
 628         u32 omap_rev = omap_revision();
 629
 630         switch (omap_rev) {
 631
 632         case OMAP5430_ES1_0:
 633         case OMAP5432_ES1_0:
 634         *prcm = &omap5_es1_prcm;
 635         *dplls_data = &omap5_dplls_es1;
 636         *omap_vcores = &omap5430_volts;
 637         *ctrl = &omap5_ctrl;
 638         break;
 639
 640         case OMAP5430_ES2_0:
 641         case OMAP5432_ES2_0:
 642         *prcm = &omap5_es2_prcm;
 643         *dplls_data = &omap5_dplls_es2;
 644         *omap_vcores = &omap5430_volts_es2;
 645         *ctrl = &omap5_ctrl;
 646         break;
 647
 648         case DRA752_ES1_0:
 649         *prcm = &dra7xx_prcm;
 650         *dplls_data = &dra7xx_dplls;
 651         *omap_vcores = &dra752_volts;
 652         *ctrl = &dra7xx_ctrl;
 653         break;
 654
 655         default:
 656                 printf("\n INVALID OMAP REVISION ");
 657         }
 658 }
 659
 660 void get_ioregs(const struct ctrl_ioregs **regs)
 661 {
 662         u32 omap_rev = omap_revision();
 663
 664         switch (omap_rev) {
 665         case OMAP5430_ES1_0:
 666         case OMAP5430_ES2_0:
 667                 *regs = &ioregs_omap5430;
 668                 break;
 669         case OMAP5432_ES1_0:
 670                 *regs = &ioregs_omap5432_es1;
 671                 break;
 672         case OMAP5432_ES2_0:
 673                 *regs = &ioregs_omap5432_es2;
 674                 break;
 675         case DRA752_ES1_0:
 676                 *regs = &ioregs_dra7xx_es1;
 677                 break;
 678
 679         default:
 680                 printf("\n INVALID OMAP REVISION ");
 681         }
 682 }