arch/arm/cpu/armv7/omap5/hw_data.c

   1 /*
   2  *
   3  * HW data initialization for OMAP5
   4  *
   5  * (C) Copyright 2013
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Sricharan R <r.sricharan@ti.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28 #include <common.h>
  29 #include <palmas.h>
  30 #include <asm/arch/omap.h>
  31 #include <asm/arch/sys_proto.h>
  32 #include <asm/omap_common.h>
  33 #include <asm/arch/clock.h>
  34 #include <asm/omap_gpio.h>
  35 #include <asm/io.h>
  36 #include <asm/emif.h>
  37
  38 struct prcm_regs const **prcm =
  39                         (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
  40 struct dplls const **dplls_data =
  41                         (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
  42 struct vcores_data const **omap_vcores =
  43                 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
  44 struct omap_sys_ctrl_regs const **ctrl =
  45         (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
  46
  47 /* OPP HIGH FREQUENCY for ES2.0 */
  48 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
  49         {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  50         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  51         {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
  52         {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  53         {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  54         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  55         {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  56 };
  57
  58 /* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
  59 static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
  60         {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  61         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  62         {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 16.8 MHz */
  63         {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 19.2 MHz */
  64         {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  65         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  66         {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}       /* 38.4 MHz */
  67 };
  68
  69 /* OPP NOM FREQUENCY for ES1.0 */
  70 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
  71         {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  72         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  73         {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 16.8 MHz */
  74         {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  75         {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  76         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  77         {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  78 };
  79
  80 /* OPP LOW FREQUENCY for ES1.0 */
  81 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
  82         {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  83         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  84         {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 16.8 MHz */
  85         {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  86         {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  87         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  88         {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  89 };
  90
  91 /* OPP LOW FREQUENCY for ES2.0 */
  92 static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
  93         {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
  94         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  95         {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
  96         {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
  97         {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  98         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  99         {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
 100 };
 101
 102 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
 103         {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
 104         {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz   */
 105         {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
 106         {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
 107         {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 26 MHz   */
 108         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 109         {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 38.4 MHz */
 110 };
 111
 112 static const struct dpll_params
 113                         core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
 114         {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 12 MHz   */
 115         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 116         {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 16.8 MHz */
 117         {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 19.2 MHz */
 118         {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 26 MHz   */
 119         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 120         {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}               /* 38.4 MHz */
 121 };
 122
 123 static const struct dpll_params
 124                         core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
 125         {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 12 MHz   */
 126         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 127         {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 16.8 MHz */
 128         {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 19.2 MHz */
 129         {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 26 MHz   */
 130         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 131         {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}                /* 38.4 MHz */
 132 };
 133
 134 static const struct dpll_params
 135                 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
 136         {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 12 MHz   */
 137         {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 20 MHz   */
 138         {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 16.8 MHz */
 139         {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 19.2 MHz */
 140         {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 26 MHz   */
 141         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 142         {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 38.4 MHz */
 143 };
 144
 145 static const struct dpll_params
 146                         core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
 147         {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 12 MHz   */
 148         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 149         {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 16.8 MHz */
 150         {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 19.2 MHz */
 151         {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 26 MHz   */
 152         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 153         {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}            /* 38.4 MHz */
 154 };
 155
 156 static const struct dpll_params
 157                         core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
 158         {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 12 MHz   */
 159         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 160         {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 16.8 MHz */
 161         {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 19.2 MHz */
 162         {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 26 MHz   */
 163         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 164         {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}             /* 38.4 MHz */
 165 };
 166
 167 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
 168         {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},             /* 12 MHz   */
 169         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 170         {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},            /* 16.8 MHz */
 171         {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},             /* 19.2 MHz */
 172         {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},           /* 26 MHz   */
 173         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 174         {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}              /* 38.4 MHz */
 175 };
 176
 177 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 178         {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},             /* 12 MHz   */
 179         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 180         {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},            /* 16.8 MHz */
 181         {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},             /* 19.2 MHz */
 182         {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},           /* 26 MHz   */
 183         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 184         {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}              /* 38.4 MHz */
 185 };
 186
 187 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
 188         {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 12 MHz   */
 189         {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 20 MHz   */
 190         {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 16.8 MHz */
 191         {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 19.2 MHz */
 192         {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},           /* 26 MHz   */
 193         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 194         {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 38.4 MHz */
 195 };
 196
 197 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
 198         {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 199         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 200         {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
 201         {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 202         {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 203         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 204         {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}           /* 38.4 MHz */
 205 };
 206
 207 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
 208         {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 209         {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz */
 210         {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
 211         {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 212         {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 213         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 214         {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 38.4 MHz */
 215 };
 216
 217 /* ABE M & N values with sys_clk as source */
 218 static const struct dpll_params
 219                 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
 220         {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
 221         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 222         {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
 223         {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 19.2 MHz */
 224         {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 26 MHz   */
 225         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 226         {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}          /* 38.4 MHz */
 227 };
 228
 229 /* ABE M & N values with 32K clock as source */
 230 static const struct dpll_params abe_dpll_params_32k_196608khz = {
 231         750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
 232 };
 233
 234 /* ABE M & N values with sysclk2(22.5792 MHz) as input */
 235 static const struct dpll_params
 236                 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
 237         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 238         {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
 239         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 16.8 MHz */
 240         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
 241         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
 242         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 243         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
 244 };
 245
 246 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
 247         {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
 248         {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 20 MHz   */
 249         {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
 250         {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
 251         {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
 252         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 253         {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
 254 };
 255
 256 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
 257         {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 12 MHz   */
 258         {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
 259         {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
 260         {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 261         {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 262         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 263         {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 38.4 MHz */
 264 };
 265
 266 struct dplls omap5_dplls_es1 = {
 267         .mpu = mpu_dpll_params_800mhz,
 268         .core = core_dpll_params_2128mhz_ddr532,
 269         .per = per_dpll_params_768mhz,
 270         .iva = iva_dpll_params_2330mhz,
 271 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 272         .abe = abe_dpll_params_sysclk_196608khz,
 273 #else
 274         .abe = &abe_dpll_params_32k_196608khz,
 275 #endif
 276         .usb = usb_dpll_params_1920mhz,
 277         .ddr = NULL
 278 };
 279
 280 struct dplls omap5_dplls_es2 = {
 281         .mpu = mpu_dpll_params_1100mhz,
 282         .core = core_dpll_params_2128mhz_ddr532_es2,
 283         .per = per_dpll_params_768mhz_es2,
 284         .iva = iva_dpll_params_2330mhz,
 285 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 286         .abe = abe_dpll_params_sysclk_196608khz,
 287 #else
 288         .abe = &abe_dpll_params_32k_196608khz,
 289 #endif
 290         .usb = usb_dpll_params_1920mhz,
 291         .ddr = NULL
 292 };
 293
 294 struct dplls dra7xx_dplls = {
 295         .mpu = mpu_dpll_params_1ghz,
 296         .core = core_dpll_params_2128mhz_dra7xx,
 297         .per = per_dpll_params_768mhz_dra7xx,
 298         .abe = abe_dpll_params_sysclk2_361267khz,
 299         .iva = iva_dpll_params_2330mhz_dra7xx,
 300         .usb = usb_dpll_params_1920mhz,
 301         .ddr = ddr_dpll_params_2128mhz,
 302 };
 303
 304 struct pmic_data palmas = {
 305         .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
 306         .step = 10000, /* 10 mV represented in uV */
 307         /*
 308          * Offset codes 1-6 all give the base voltage in Palmas
 309          * Offset code 0 switches OFF the SMPS
 310          */
 311         .start_code = 6,
 312         .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
 313         .pmic_bus_init  = sri2c_init,
 314         .pmic_write     = omap_vc_bypass_send_value,
 315 };
 316
 317 struct pmic_data tps659038 = {
 318         .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
 319         .step = 10000, /* 10 mV represented in uV */
 320         /*
 321          * Offset codes 1-6 all give the base voltage in Palmas
 322          * Offset code 0 switches OFF the SMPS
 323          */
 324         .start_code = 6,
 325         .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
 326         .pmic_bus_init  = gpi2c_init,
 327         .pmic_write     = palmas_i2c_write_u8,
 328 };
 329
 330 struct vcores_data omap5430_volts = {
 331         .mpu.value = VDD_MPU,
 332         .mpu.addr = SMPS_REG_ADDR_12_MPU,
 333         .mpu.pmic = &palmas,
 334
 335         .core.value = VDD_CORE,
 336         .core.addr = SMPS_REG_ADDR_8_CORE,
 337         .core.pmic = &palmas,
 338
 339         .mm.value = VDD_MM,
 340         .mm.addr = SMPS_REG_ADDR_45_IVA,
 341         .mm.pmic = &palmas,
 342 };
 343
 344 struct vcores_data omap5430_volts_es2 = {
 345         .mpu.value = VDD_MPU_ES2,
 346         .mpu.addr = SMPS_REG_ADDR_12_MPU,
 347         .mpu.pmic = &palmas,
 348
 349         .core.value = VDD_CORE_ES2,
 350         .core.addr = SMPS_REG_ADDR_8_CORE,
 351         .core.pmic = &palmas,
 352
 353         .mm.value = VDD_MM_ES2,
 354         .mm.addr = SMPS_REG_ADDR_45_IVA,
 355         .mm.pmic = &palmas,
 356 };
 357
 358 struct vcores_data dra752_volts = {
 359         .mpu.value      = VDD_MPU_DRA752,
 360         .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU_NOM,
 361         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 362         .mpu.addr       = TPS659038_REG_ADDR_SMPS12_MPU,
 363         .mpu.pmic       = &tps659038,
 364
 365         .eve.value      = VDD_EVE_DRA752,
 366         .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 367         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 368         .eve.addr       = TPS659038_REG_ADDR_SMPS45_EVE,
 369         .eve.pmic       = &tps659038,
 370
 371         .gpu.value      = VDD_GPU_DRA752,
 372         .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU_NOM,
 373         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 374         .gpu.addr       = TPS659038_REG_ADDR_SMPS6_GPU,
 375         .gpu.pmic       = &tps659038,
 376
 377         .core.value     = VDD_CORE_DRA752,
 378         .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
 379         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 380         .core.addr      = TPS659038_REG_ADDR_SMPS7_CORE,
 381         .core.pmic      = &tps659038,
 382
 383         .iva.value      = VDD_IVA_DRA752,
 384         .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA_NOM,
 385         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 386         .iva.addr       = TPS659038_REG_ADDR_SMPS8_IVA,
 387         .iva.pmic       = &tps659038,
 388 };
 389
 390 /*
 391  * Enable essential clock domains, modules and
 392  * do some additional special settings needed
 393  */
 394 void enable_basic_clocks(void)
 395 {
 396         u32 const clk_domains_essential[] = {
 397                 (*prcm)->cm_l4per_clkstctrl,
 398                 (*prcm)->cm_l3init_clkstctrl,
 399                 (*prcm)->cm_memif_clkstctrl,
 400                 (*prcm)->cm_l4cfg_clkstctrl,
 401                 0
 402         };
 403
 404         u32 const clk_modules_hw_auto_essential[] = {
 405                 (*prcm)->cm_l3_gpmc_clkctrl,
 406                 (*prcm)->cm_memif_emif_1_clkctrl,
 407                 (*prcm)->cm_memif_emif_2_clkctrl,
 408                 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
 409                 (*prcm)->cm_wkup_gpio1_clkctrl,
 410                 (*prcm)->cm_l4per_gpio2_clkctrl,
 411                 (*prcm)->cm_l4per_gpio3_clkctrl,
 412                 (*prcm)->cm_l4per_gpio4_clkctrl,
 413                 (*prcm)->cm_l4per_gpio5_clkctrl,
 414                 (*prcm)->cm_l4per_gpio6_clkctrl,
 415                 (*prcm)->cm_l4per_gpio7_clkctrl,
 416                 (*prcm)->cm_l4per_gpio8_clkctrl,
 417                 0
 418         };
 419
 420         u32 const clk_modules_explicit_en_essential[] = {
 421                 (*prcm)->cm_wkup_gptimer1_clkctrl,
 422                 (*prcm)->cm_l3init_hsmmc1_clkctrl,
 423                 (*prcm)->cm_l3init_hsmmc2_clkctrl,
 424                 (*prcm)->cm_l4per_gptimer2_clkctrl,
 425                 (*prcm)->cm_wkup_wdtimer2_clkctrl,
 426                 (*prcm)->cm_l4per_uart3_clkctrl,
 427                 (*prcm)->cm_l4per_i2c1_clkctrl,
 428                 0
 429         };
 430
 431         /* Enable optional additional functional clock for GPIO4 */
 432         setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
 433                         GPIO4_CLKCTRL_OPTFCLKEN_MASK);
 434
 435         /* Enable 96 MHz clock for MMC1 & MMC2 */
 436         setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 437                         HSMMC_CLKCTRL_CLKSEL_MASK);
 438         setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 439                         HSMMC_CLKCTRL_CLKSEL_MASK);
 440
 441         /* Set the correct clock dividers for mmc */
 442         setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 443                         HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 444         setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 445                         HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 446
 447         /* Select 32KHz clock as the source of GPTIMER1 */
 448         setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
 449                         GPTIMER1_CLKCTRL_CLKSEL_MASK);
 450
 451         do_enable_clocks(clk_domains_essential,
 452                          clk_modules_hw_auto_essential,
 453                          clk_modules_explicit_en_essential,
 454                          1);
 455
 456         /* Enable SCRM OPT clocks for PER and CORE dpll */
 457         setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 458                         OPTFCLKEN_SCRM_PER_MASK);
 459         setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 460                         OPTFCLKEN_SCRM_CORE_MASK);
 461 }
 462
 463 void enable_basic_uboot_clocks(void)
 464 {
 465         u32 const clk_domains_essential[] = {
 466                 0
 467         };
 468
 469         u32 const clk_modules_hw_auto_essential[] = {
 470                 (*prcm)->cm_l3init_hsusbtll_clkctrl,
 471                 0
 472         };
 473
 474         u32 const clk_modules_explicit_en_essential[] = {
 475                 (*prcm)->cm_l4per_mcspi1_clkctrl,
 476                 (*prcm)->cm_l4per_i2c2_clkctrl,
 477                 (*prcm)->cm_l4per_i2c3_clkctrl,
 478                 (*prcm)->cm_l4per_i2c4_clkctrl,
 479                 (*prcm)->cm_l4per_i2c5_clkctrl,
 480                 (*prcm)->cm_l3init_hsusbhost_clkctrl,
 481                 (*prcm)->cm_l3init_fsusb_clkctrl,
 482                 0
 483         };
 484
 485         do_enable_clocks(clk_domains_essential,
 486                          clk_modules_hw_auto_essential,
 487                          clk_modules_explicit_en_essential,
 488                          1);
 489 }
 490
 491 /*
 492  * Enable non-essential clock domains, modules and
 493  * do some additional special settings needed
 494  */
 495 void enable_non_essential_clocks(void)
 496 {
 497         u32 const clk_domains_non_essential[] = {
 498                 (*prcm)->cm_mpu_m3_clkstctrl,
 499                 (*prcm)->cm_ivahd_clkstctrl,
 500                 (*prcm)->cm_dsp_clkstctrl,
 501                 (*prcm)->cm_dss_clkstctrl,
 502                 (*prcm)->cm_sgx_clkstctrl,
 503                 (*prcm)->cm1_abe_clkstctrl,
 504                 (*prcm)->cm_c2c_clkstctrl,
 505                 (*prcm)->cm_cam_clkstctrl,
 506                 (*prcm)->cm_dss_clkstctrl,
 507                 (*prcm)->cm_sdma_clkstctrl,
 508                 0
 509         };
 510
 511         u32 const clk_modules_hw_auto_non_essential[] = {
 512                 (*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
 513                 (*prcm)->cm_ivahd_ivahd_clkctrl,
 514                 (*prcm)->cm_ivahd_sl2_clkctrl,
 515                 (*prcm)->cm_dsp_dsp_clkctrl,
 516                 (*prcm)->cm_l3instr_l3_3_clkctrl,
 517                 (*prcm)->cm_l3instr_l3_instr_clkctrl,
 518                 (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
 519                 (*prcm)->cm_l3init_hsi_clkctrl,
 520                 (*prcm)->cm_l4per_hdq1w_clkctrl,
 521                 0
 522         };
 523
 524         u32 const clk_modules_explicit_en_non_essential[] = {
 525                 (*prcm)->cm1_abe_aess_clkctrl,
 526                 (*prcm)->cm1_abe_pdm_clkctrl,
 527                 (*prcm)->cm1_abe_dmic_clkctrl,
 528                 (*prcm)->cm1_abe_mcasp_clkctrl,
 529                 (*prcm)->cm1_abe_mcbsp1_clkctrl,
 530                 (*prcm)->cm1_abe_mcbsp2_clkctrl,
 531                 (*prcm)->cm1_abe_mcbsp3_clkctrl,
 532                 (*prcm)->cm1_abe_slimbus_clkctrl,
 533                 (*prcm)->cm1_abe_timer5_clkctrl,
 534                 (*prcm)->cm1_abe_timer6_clkctrl,
 535                 (*prcm)->cm1_abe_timer7_clkctrl,
 536                 (*prcm)->cm1_abe_timer8_clkctrl,
 537                 (*prcm)->cm1_abe_wdt3_clkctrl,
 538                 (*prcm)->cm_l4per_gptimer9_clkctrl,
 539                 (*prcm)->cm_l4per_gptimer10_clkctrl,
 540                 (*prcm)->cm_l4per_gptimer11_clkctrl,
 541                 (*prcm)->cm_l4per_gptimer3_clkctrl,
 542                 (*prcm)->cm_l4per_gptimer4_clkctrl,
 543                 (*prcm)->cm_l4per_mcspi2_clkctrl,
 544                 (*prcm)->cm_l4per_mcspi3_clkctrl,
 545                 (*prcm)->cm_l4per_mcspi4_clkctrl,
 546                 (*prcm)->cm_l4per_mmcsd3_clkctrl,
 547                 (*prcm)->cm_l4per_mmcsd4_clkctrl,
 548                 (*prcm)->cm_l4per_mmcsd5_clkctrl,
 549                 (*prcm)->cm_l4per_uart1_clkctrl,
 550                 (*prcm)->cm_l4per_uart2_clkctrl,
 551                 (*prcm)->cm_l4per_uart4_clkctrl,
 552                 (*prcm)->cm_wkup_keyboard_clkctrl,
 553                 (*prcm)->cm_wkup_wdtimer2_clkctrl,
 554                 (*prcm)->cm_cam_iss_clkctrl,
 555                 (*prcm)->cm_cam_fdif_clkctrl,
 556                 (*prcm)->cm_dss_dss_clkctrl,
 557                 (*prcm)->cm_sgx_sgx_clkctrl,
 558                 0
 559         };
 560
 561         /* Enable optional functional clock for ISS */
 562         setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
 563
 564         /* Enable all optional functional clocks of DSS */
 565         setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
 566
 567         do_enable_clocks(clk_domains_non_essential,
 568                          clk_modules_hw_auto_non_essential,
 569                          clk_modules_explicit_en_non_essential,
 570                          0);
 571
 572         /* Put camera module in no sleep mode */
 573         clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
 574                         MODULE_CLKCTRL_MODULEMODE_MASK,
 575                         CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
 576                         MODULE_CLKCTRL_MODULEMODE_SHIFT);
 577 }
 578
 579 const struct ctrl_ioregs ioregs_omap5430 = {
 580         .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
 581         .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
 582         .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
 583         .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
 584         .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
 585 };
 586
 587 const struct ctrl_ioregs ioregs_omap5432_es1 = {
 588         .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
 589         .ctrl_lpddr2ch = 0x0,
 590         .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
 591         .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
 592         .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
 593         .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
 594         .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 595 };
 596
 597 const struct ctrl_ioregs ioregs_omap5432_es2 = {
 598         .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
 599         .ctrl_lpddr2ch = 0x0,
 600         .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
 601         .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
 602         .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
 603         .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
 604         .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 605 };
 606
 607 const struct ctrl_ioregs ioregs_dra7xx_es1 = {
 608         .ctrl_ddrch = 0x40404040,
 609         .ctrl_lpddr2ch = 0x40404040,
 610         .ctrl_ddr3ch = 0x80808080,
 611         .ctrl_ddrio_0 = 0xbae8c631,
 612         .ctrl_ddrio_1 = 0xb46318d8,
 613         .ctrl_ddrio_2 = 0x84210000,
 614         .ctrl_emif_sdram_config_ext = 0xb2c00000,
 615         .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 616 };
 617
 618 void hw_data_init(void)
 619 {
 620         u32 omap_rev = omap_revision();
 621
 622         switch (omap_rev) {
 623
 624         case OMAP5430_ES1_0:
 625         case OMAP5432_ES1_0:
 626         *prcm = &omap5_es1_prcm;
 627         *dplls_data = &omap5_dplls_es1;
 628         *omap_vcores = &omap5430_volts;
 629         *ctrl = &omap5_ctrl;
 630         break;
 631
 632         case OMAP5430_ES2_0:
 633         case OMAP5432_ES2_0:
 634         *prcm = &omap5_es2_prcm;
 635         *dplls_data = &omap5_dplls_es2;
 636         *omap_vcores = &omap5430_volts_es2;
 637         *ctrl = &omap5_ctrl;
 638         break;
 639
 640         case DRA752_ES1_0:
 641         *prcm = &dra7xx_prcm;
 642         *dplls_data = &dra7xx_dplls;
 643         *omap_vcores = &dra752_volts;
 644         *ctrl = &dra7xx_ctrl;
 645         break;
 646
 647         default:
 648                 printf("\n INVALID OMAP REVISION ");
 649         }
 650 }
 651
 652 void get_ioregs(const struct ctrl_ioregs **regs)
 653 {
 654         u32 omap_rev = omap_revision();
 655
 656         switch (omap_rev) {
 657         case OMAP5430_ES1_0:
 658         case OMAP5430_ES2_0:
 659                 *regs = &ioregs_omap5430;
 660                 break;
 661         case OMAP5432_ES1_0:
 662                 *regs = &ioregs_omap5432_es1;
 663                 break;
 664         case OMAP5432_ES2_0:
 665                 *regs = &ioregs_omap5432_es2;
 666                 break;
 667         case DRA752_ES1_0:
 668                 *regs = &ioregs_dra7xx_es1;
 669                 break;
 670
 671         default:
 672                 printf("\n INVALID OMAP REVISION ");
 673         }
 674 }