arch/arm/cpu/armv7/start.S

   1 /*
   2  * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
   3  *
   4  * Copyright (c) 2004   Texas Instruments <r-woodruff2@ti.com>
   5  *
   6  * Copyright (c) 2001   Marius Gröger <mag@sysgo.de>
   7  * Copyright (c) 2002   Alex Züpke <azu@sysgo.de>
   8  * Copyright (c) 2002   Gary Jennejohn <garyj@denx.de>
   9  * Copyright (c) 2003   Richard Woodruff <r-woodruff2@ti.com>
  10  * Copyright (c) 2003   Kshitij <kshitij@ti.com>
  11  * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 #include <asm-offsets.h>
  33 #include <config.h>
  34 #include <version.h>
  35
  36 .globl _start
  37 _start: b       reset
  38         ldr     pc, _undefined_instruction
  39         ldr     pc, _software_interrupt
  40         ldr     pc, _prefetch_abort
  41         ldr     pc, _data_abort
  42         ldr     pc, _not_used
  43         ldr     pc, _irq
  44         ldr     pc, _fiq
  45
  46 _undefined_instruction: .word undefined_instruction
  47 _software_interrupt:    .word software_interrupt
  48 _prefetch_abort:        .word prefetch_abort
  49 _data_abort:            .word data_abort
  50 _not_used:              .word not_used
  51 _irq:                   .word irq
  52 _fiq:                   .word fiq
  53 _pad:                   .word 0x12345678 /* now 16*4=64 */
  54 .global _end_vect
  55 _end_vect:
  56
  57         .balignl 16,0xdeadbeef
  58 /*************************************************************************
  59  *
  60  * Startup Code (reset vector)
  61  *
  62  * do important init only if we don't start from memory!
  63  * setup Memory and board specific bits prior to relocation.
  64  * relocate armboot to ram
  65  * setup stack
  66  *
  67  *************************************************************************/
  68
  69 .globl _TEXT_BASE
  70 _TEXT_BASE:
  71         .word   CONFIG_SYS_TEXT_BASE
  72
  73 #ifdef CONFIG_TEGRA2
  74 /*
  75  * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
  76  * U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
  77  * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
  78  * to pick up its reset vector, which points here.
  79  */
  80 .globl _armboot_start
  81 _armboot_start:
  82         .word _start
  83 #endif
  84
  85 /*
  86  * These are defined in the board-specific linker script.
  87  */
  88 .globl _bss_start_ofs
  89 _bss_start_ofs:
  90         .word __bss_start - _start
  91
  92 .globl _bss_end_ofs
  93 _bss_end_ofs:
  94         .word __bss_end__ - _start
  95
  96 .globl _end_ofs
  97 _end_ofs:
  98         .word _end - _start
  99
 100 #ifdef CONFIG_USE_IRQ
 101 /* IRQ stack memory (calculated at run-time) */
 102 .globl IRQ_STACK_START
 103 IRQ_STACK_START:
 104         .word   0x0badc0de
 105
 106 /* IRQ stack memory (calculated at run-time) */
 107 .globl FIQ_STACK_START
 108 FIQ_STACK_START:
 109         .word 0x0badc0de
 110 #endif
 111
 112 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 113 .globl IRQ_STACK_START_IN
 114 IRQ_STACK_START_IN:
 115         .word   0x0badc0de
 116
 117 /*
 118  * the actual reset code
 119  */
 120
 121 reset:
 122         /*
 123          * set the cpu to SVC32 mode
 124          */
 125         mrs     r0, cpsr
 126         bic     r0, r0, #0x1f
 127         orr     r0, r0, #0xd3
 128         msr     cpsr,r0
 129
 130 #if defined(CONFIG_OMAP34XX)
 131         /* Copy vectors to mask ROM indirect addr */
 132         adr     r0, _start              @ r0 <- current position of code
 133         add     r0, r0, #4              @ skip reset vector
 134         mov     r2, #64                 @ r2 <- size to copy
 135         add     r2, r0, r2              @ r2 <- source end address
 136         mov     r1, #SRAM_OFFSET0       @ build vect addr
 137         mov     r3, #SRAM_OFFSET1
 138         add     r1, r1, r3
 139         mov     r3, #SRAM_OFFSET2
 140         add     r1, r1, r3
 141 next:
 142         ldmia   r0!, {r3 - r10}         @ copy from source address [r0]
 143         stmia   r1!, {r3 - r10}         @ copy to   target address [r1]
 144         cmp     r0, r2                  @ until source end address [r2]
 145         bne     next                    @ loop until equal */
 146 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
 147         /* No need to copy/exec the clock code - DPLL adjust already done
 148          * in NAND/oneNAND Boot.
 149          */
 150         bl      cpy_clk_code            @ put dpll adjust code behind vectors
 151 #endif /* NAND Boot */
 152 #endif
 153         /* the mask ROM code should have PLL and others stable */
 154 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 155         bl      cpu_init_crit
 156 #endif
 157
 158 /* Set stackpointer in internal RAM to call board_init_f */
 159 call_board_init_f:
 160         ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 161         bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
 162         ldr     r0,=0x00000000
 163         bl      board_init_f
 164
 165 /*------------------------------------------------------------------------------*/
 166
 167 /*
 168  * void relocate_code (addr_sp, gd, addr_moni)
 169  *
 170  * This "function" does not return, instead it continues in RAM
 171  * after relocating the monitor code.
 172  *
 173  */
 174         .globl  relocate_code
 175 relocate_code:
 176         mov     r4, r0  /* save addr_sp */
 177         mov     r5, r1  /* save addr of gd */
 178         mov     r6, r2  /* save addr of destination */
 179
 180         /* Set up the stack                                                 */
 181 stack_setup:
 182         mov     sp, r4
 183
 184         adr     r0, _start
 185 #ifndef CONFIG_SPL_BUILD
 186         cmp     r0, r6
 187         beq     clear_bss               /* skip relocation */
 188 #endif
 189         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 190         ldr     r3, _bss_start_ofs
 191         add     r2, r0, r3              /* r2 <- source end address         */
 192
 193 copy_loop:
 194         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 195         stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 196         cmp     r0, r2                  /* until source end address [r2]    */
 197         blo     copy_loop
 198
 199 #ifndef CONFIG_SPL_BUILD
 200         /*
 201          * fix .rel.dyn relocations
 202          */
 203         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 204         sub     r9, r6, r0              /* r9 <- relocation offset */
 205         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 206         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 207         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 208         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 209         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 210         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 211 fixloop:
 212         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 213         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 214         ldr     r1, [r2, #4]
 215         and     r7, r1, #0xff
 216         cmp     r7, #23                 /* relative fixup? */
 217         beq     fixrel
 218         cmp     r7, #2                  /* absolute fixup? */
 219         beq     fixabs
 220         /* ignore unknown type of fixup */
 221         b       fixnext
 222 fixabs:
 223         /* absolute fix: set location to (offset) symbol value */
 224         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 225         add     r1, r10, r1             /* r1 <- address of symbol in table */
 226         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 227         add     r1, r1, r9              /* r1 <- relocated sym addr */
 228         b       fixnext
 229 fixrel:
 230         /* relative fix: increase location by offset */
 231         ldr     r1, [r0]
 232         add     r1, r1, r9
 233 fixnext:
 234         str     r1, [r0]
 235         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 236         cmp     r2, r3
 237         blo     fixloop
 238
 239 clear_bss:
 240         ldr     r0, _bss_start_ofs
 241         ldr     r1, _bss_end_ofs
 242         mov     r4, r6                  /* reloc addr */
 243         add     r0, r0, r4
 244         add     r1, r1, r4
 245         mov     r2, #0x00000000         /* clear                            */
 246
 247 clbss_l:str     r2, [r0]                /* clear loop...                    */
 248         add     r0, r0, #4
 249         cmp     r0, r1
 250         bne     clbss_l
 251 #endif  /* #ifndef CONFIG_SPL_BUILD */
 252
 253 /*
 254  * We are done. Do not return, instead branch to second part of board
 255  * initialization, now running from RAM.
 256  */
 257 jump_2_ram:
 258 /*
 259  * If I-cache is enabled invalidate it
 260  */
 261 #ifndef CONFIG_SYS_ICACHE_OFF
 262         mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
 263         mcr     p15, 0, r0, c7, c10, 4  @ DSB
 264         mcr     p15, 0, r0, c7, c5, 4   @ ISB
 265 #endif
 266         ldr     r0, _board_init_r_ofs
 267         adr     r1, _start
 268         add     lr, r0, r1
 269         add     lr, lr, r9
 270         /* setup parameters for board_init_r */
 271         mov     r0, r5          /* gd_t */
 272         mov     r1, r6          /* dest_addr */
 273         /* jump to it ... */
 274         mov     pc, lr
 275
 276 _board_init_r_ofs:
 277         .word board_init_r - _start
 278
 279 _rel_dyn_start_ofs:
 280         .word __rel_dyn_start - _start
 281 _rel_dyn_end_ofs:
 282         .word __rel_dyn_end - _start
 283 _dynsym_start_ofs:
 284         .word __dynsym_start - _start
 285
 286 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 287 /*************************************************************************
 288  *
 289  * CPU_init_critical registers
 290  *
 291  * setup important registers
 292  * setup memory timing
 293  *
 294  *************************************************************************/
 295 cpu_init_crit:
 296         /*
 297          * Invalidate L1 I/D
 298          */
 299         mov     r0, #0                  @ set up for MCR
 300         mcr     p15, 0, r0, c8, c7, 0   @ invalidate TLBs
 301         mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
 302         mcr     p15, 0, r0, c7, c5, 6   @ invalidate BP array
 303         mcr     p15, 0, r0, c7, c10, 4  @ DSB
 304         mcr     p15, 0, r0, c7, c5, 4   @ ISB
 305
 306         /*
 307          * disable MMU stuff and caches
 308          */
 309         mrc     p15, 0, r0, c1, c0, 0
 310         bic     r0, r0, #0x00002000     @ clear bits 13 (--V-)
 311         bic     r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)
 312         orr     r0, r0, #0x00000002     @ set bit 1 (--A-) Align
 313         orr     r0, r0, #0x00000800     @ set bit 11 (Z---) BTB
 314 #ifdef CONFIG_SYS_ICACHE_OFF
 315         bic     r0, r0, #0x00001000     @ clear bit 12 (I) I-cache
 316 #else
 317         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-cache
 318 #endif
 319         mcr     p15, 0, r0, c1, c0, 0
 320
 321         /*
 322          * Jump to board specific initialization...
 323          * The Mask ROM will have already initialized
 324          * basic memory. Go here to bump up clock rate and handle
 325          * wake up conditions.
 326          */
 327         mov     ip, lr                  @ persevere link reg across call
 328         bl      lowlevel_init           @ go setup pll,mux,memory
 329         mov     lr, ip                  @ restore link
 330         mov     pc, lr                  @ back to my caller
 331 #endif
 332 /*
 333  *************************************************************************
 334  *
 335  * Interrupt handling
 336  *
 337  *************************************************************************
 338  */
 339 @
 340 @ IRQ stack frame.
 341 @
 342 #define S_FRAME_SIZE    72
 343
 344 #define S_OLD_R0        68
 345 #define S_PSR           64
 346 #define S_PC            60
 347 #define S_LR            56
 348 #define S_SP            52
 349
 350 #define S_IP            48
 351 #define S_FP            44
 352 #define S_R10           40
 353 #define S_R9            36
 354 #define S_R8            32
 355 #define S_R7            28
 356 #define S_R6            24
 357 #define S_R5            20
 358 #define S_R4            16
 359 #define S_R3            12
 360 #define S_R2            8
 361 #define S_R1            4
 362 #define S_R0            0
 363
 364 #define MODE_SVC 0x13
 365 #define I_BIT    0x80
 366
 367 /*
 368  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 369  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 370  */
 371
 372         .macro  bad_save_user_regs
 373         sub     sp, sp, #S_FRAME_SIZE           @ carve out a frame on current
 374                                                 @ user stack
 375         stmia   sp, {r0 - r12}                  @ Save user registers (now in
 376                                                 @ svc mode) r0-r12
 377         ldr     r2, IRQ_STACK_START_IN          @ set base 2 words into abort
 378                                                 @ stack
 379         ldmia   r2, {r2 - r3}                   @ get values for "aborted" pc
 380                                                 @ and cpsr (into parm regs)
 381         add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
 382
 383         add     r5, sp, #S_SP
 384         mov     r1, lr
 385         stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 386         mov     r0, sp                          @ save current stack into r0
 387                                                 @ (param register)
 388         .endm
 389
 390         .macro  irq_save_user_regs
 391         sub     sp, sp, #S_FRAME_SIZE
 392         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 393         add     r8, sp, #S_PC                   @ !! R8 NEEDS to be saved !!
 394                                                 @ a reserved stack spot would
 395                                                 @ be good.
 396         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 397         str     lr, [r8, #0]                    @ Save calling PC
 398         mrs     r6, spsr
 399         str     r6, [r8, #4]                    @ Save CPSR
 400         str     r0, [r8, #8]                    @ Save OLD_R0
 401         mov     r0, sp
 402         .endm
 403
 404         .macro  irq_restore_user_regs
 405         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 406         mov     r0, r0
 407         ldr     lr, [sp, #S_PC]                 @ Get PC
 408         add     sp, sp, #S_FRAME_SIZE
 409         subs    pc, lr, #4                      @ return & move spsr_svc into
 410                                                 @ cpsr
 411         .endm
 412
 413         .macro get_bad_stack
 414         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack (enter
 415                                                 @ in banked mode)
 416
 417         str     lr, [r13]                       @ save caller lr in position 0
 418                                                 @ of saved stack
 419         mrs     lr, spsr                        @ get the spsr
 420         str     lr, [r13, #4]                   @ save spsr in position 1 of
 421                                                 @ saved stack
 422
 423         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 424         @ msr   spsr_c, r13
 425         msr     spsr, r13                       @ switch modes, make sure
 426                                                 @ moves will execute
 427         mov     lr, pc                          @ capture return pc
 428         movs    pc, lr                          @ jump to next instruction &
 429                                                 @ switch modes.
 430         .endm
 431
 432         .macro get_bad_stack_swi
 433         sub     r13, r13, #4                    @ space on current stack for
 434                                                 @ scratch reg.
 435         str     r0, [r13]                       @ save R0's value.
 436         ldr     r0, IRQ_STACK_START_IN          @ get data regions start
 437                                                 @ spots for abort stack
 438         str     lr, [r0]                        @ save caller lr in position 0
 439                                                 @ of saved stack
 440         mrs     r0, spsr                        @ get the spsr
 441         str     lr, [r0, #4]                    @ save spsr in position 1 of
 442                                                 @ saved stack
 443         ldr     r0, [r13]                       @ restore r0
 444         add     r13, r13, #4                    @ pop stack entry
 445         .endm
 446
 447         .macro get_irq_stack                    @ setup IRQ stack
 448         ldr     sp, IRQ_STACK_START
 449         .endm
 450
 451         .macro get_fiq_stack                    @ setup FIQ stack
 452         ldr     sp, FIQ_STACK_START
 453         .endm
 454
 455 /*
 456  * exception handlers
 457  */
 458         .align  5
 459 undefined_instruction:
 460         get_bad_stack
 461         bad_save_user_regs
 462         bl      do_undefined_instruction
 463
 464         .align  5
 465 software_interrupt:
 466         get_bad_stack_swi
 467         bad_save_user_regs
 468         bl      do_software_interrupt
 469
 470         .align  5
 471 prefetch_abort:
 472         get_bad_stack
 473         bad_save_user_regs
 474         bl      do_prefetch_abort
 475
 476         .align  5
 477 data_abort:
 478         get_bad_stack
 479         bad_save_user_regs
 480         bl      do_data_abort
 481
 482         .align  5
 483 not_used:
 484         get_bad_stack
 485         bad_save_user_regs
 486         bl      do_not_used
 487
 488 #ifdef CONFIG_USE_IRQ
 489
 490         .align  5
 491 irq:
 492         get_irq_stack
 493         irq_save_user_regs
 494         bl      do_irq
 495         irq_restore_user_regs
 496
 497         .align  5
 498 fiq:
 499         get_fiq_stack
 500         /* someone ought to write a more effective fiq_save_user_regs */
 501         irq_save_user_regs
 502         bl      do_fiq
 503         irq_restore_user_regs
 504
 505 #else
 506
 507         .align  5
 508 irq:
 509         get_bad_stack
 510         bad_save_user_regs
 511         bl      do_irq
 512
 513         .align  5
 514 fiq:
 515         get_bad_stack
 516         bad_save_user_regs
 517         bl      do_fiq
 518
 519 #endif