arch/arm/cpu/armv7/start.S

   1 /*
   2  * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
   3  *
   4  * Copyright (c) 2004   Texas Instruments <r-woodruff2@ti.com>
   5  *
   6  * Copyright (c) 2001   Marius Gröger <mag@sysgo.de>
   7  * Copyright (c) 2002   Alex Züpke <azu@sysgo.de>
   8  * Copyright (c) 2002   Gary Jennejohn <garyj@denx.de>
   9  * Copyright (c) 2003   Richard Woodruff <r-woodruff2@ti.com>
  10  * Copyright (c) 2003   Kshitij <kshitij@ti.com>
  11  * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 #include <asm-offsets.h>
  33 #include <config.h>
  34 #include <version.h>
  35
  36 .globl _start
  37 _start: b       reset
  38         ldr     pc, _undefined_instruction
  39         ldr     pc, _software_interrupt
  40         ldr     pc, _prefetch_abort
  41         ldr     pc, _data_abort
  42         ldr     pc, _not_used
  43         ldr     pc, _irq
  44         ldr     pc, _fiq
  45
  46 _undefined_instruction: .word undefined_instruction
  47 _software_interrupt:    .word software_interrupt
  48 _prefetch_abort:        .word prefetch_abort
  49 _data_abort:            .word data_abort
  50 _not_used:              .word not_used
  51 _irq:                   .word irq
  52 _fiq:                   .word fiq
  53 _pad:                   .word 0x12345678 /* now 16*4=64 */
  54 .global _end_vect
  55 _end_vect:
  56
  57         .balignl 16,0xdeadbeef
  58 /*************************************************************************
  59  *
  60  * Startup Code (reset vector)
  61  *
  62  * do important init only if we don't start from memory!
  63  * setup Memory and board specific bits prior to relocation.
  64  * relocate armboot to ram
  65  * setup stack
  66  *
  67  *************************************************************************/
  68
  69 .globl _TEXT_BASE
  70 _TEXT_BASE:
  71         .word   CONFIG_SYS_TEXT_BASE
  72
  73 /*
  74  * These are defined in the board-specific linker script.
  75  */
  76 .globl _bss_start_ofs
  77 _bss_start_ofs:
  78         .word __bss_start - _start
  79
  80 .globl _bss_end_ofs
  81 _bss_end_ofs:
  82         .word _end - _start
  83
  84 #ifdef CONFIG_USE_IRQ
  85 /* IRQ stack memory (calculated at run-time) */
  86 .globl IRQ_STACK_START
  87 IRQ_STACK_START:
  88         .word   0x0badc0de
  89
  90 /* IRQ stack memory (calculated at run-time) */
  91 .globl FIQ_STACK_START
  92 FIQ_STACK_START:
  93         .word 0x0badc0de
  94 #endif
  95
  96 /* IRQ stack memory (calculated at run-time) + 8 bytes */
  97 .globl IRQ_STACK_START_IN
  98 IRQ_STACK_START_IN:
  99         .word   0x0badc0de
 100
 101 /*
 102  * the actual reset code
 103  */
 104
 105 reset:
 106         /*
 107          * set the cpu to SVC32 mode
 108          */
 109         mrs     r0, cpsr
 110         bic     r0, r0, #0x1f
 111         orr     r0, r0, #0xd3
 112         msr     cpsr,r0
 113
 114 #if (CONFIG_OMAP34XX)
 115         /* Copy vectors to mask ROM indirect addr */
 116         adr     r0, _start              @ r0 <- current position of code
 117         add     r0, r0, #4              @ skip reset vector
 118         mov     r2, #64                 @ r2 <- size to copy
 119         add     r2, r0, r2              @ r2 <- source end address
 120         mov     r1, #SRAM_OFFSET0       @ build vect addr
 121         mov     r3, #SRAM_OFFSET1
 122         add     r1, r1, r3
 123         mov     r3, #SRAM_OFFSET2
 124         add     r1, r1, r3
 125 next:
 126         ldmia   r0!, {r3 - r10}         @ copy from source address [r0]
 127         stmia   r1!, {r3 - r10}         @ copy to   target address [r1]
 128         cmp     r0, r2                  @ until source end address [r2]
 129         bne     next                    @ loop until equal */
 130 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
 131         /* No need to copy/exec the clock code - DPLL adjust already done
 132          * in NAND/oneNAND Boot.
 133          */
 134         bl      cpy_clk_code            @ put dpll adjust code behind vectors
 135 #endif /* NAND Boot */
 136 #endif
 137         /* the mask ROM code should have PLL and others stable */
 138 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 139         bl      cpu_init_crit
 140 #endif
 141
 142 /* Set stackpointer in internal RAM to call board_init_f */
 143 call_board_init_f:
 144         ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 145         bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
 146         ldr     r0,=0x00000000
 147         bl      board_init_f
 148
 149 /*------------------------------------------------------------------------------*/
 150
 151 /*
 152  * void relocate_code (addr_sp, gd, addr_moni)
 153  *
 154  * This "function" does not return, instead it continues in RAM
 155  * after relocating the monitor code.
 156  *
 157  */
 158         .globl  relocate_code
 159 relocate_code:
 160         mov     r4, r0  /* save addr_sp */
 161         mov     r5, r1  /* save addr of gd */
 162         mov     r6, r2  /* save addr of destination */
 163
 164         /* Set up the stack                                                 */
 165 stack_setup:
 166         mov     sp, r4
 167
 168         adr     r0, _start
 169 #ifndef CONFIG_PRELOADER
 170         cmp     r0, r6
 171         beq     clear_bss               /* skip relocation */
 172 #endif
 173         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 174         ldr     r3, _bss_start_ofs
 175         add     r2, r0, r3              /* r2 <- source end address         */
 176
 177 copy_loop:
 178         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 179         stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 180         cmp     r0, r2                  /* until source end address [r2]    */
 181         blo     copy_loop
 182
 183 #ifndef CONFIG_PRELOADER
 184         /*
 185          * fix .rel.dyn relocations
 186          */
 187         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 188         sub     r9, r6, r0              /* r9 <- relocation offset */
 189         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 190         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 191         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 192         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 193         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 194         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 195 fixloop:
 196         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 197         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 198         ldr     r1, [r2, #4]
 199         and     r7, r1, #0xff
 200         cmp     r7, #23                 /* relative fixup? */
 201         beq     fixrel
 202         cmp     r7, #2                  /* absolute fixup? */
 203         beq     fixabs
 204         /* ignore unknown type of fixup */
 205         b       fixnext
 206 fixabs:
 207         /* absolute fix: set location to (offset) symbol value */
 208         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 209         add     r1, r10, r1             /* r1 <- address of symbol in table */
 210         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 211         add     r1, r1, r9              /* r1 <- relocated sym addr */
 212         b       fixnext
 213 fixrel:
 214         /* relative fix: increase location by offset */
 215         ldr     r1, [r0]
 216         add     r1, r1, r9
 217 fixnext:
 218         str     r1, [r0]
 219         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 220         cmp     r2, r3
 221         blo     fixloop
 222
 223 clear_bss:
 224         ldr     r0, _bss_start_ofs
 225         ldr     r1, _bss_end_ofs
 226         mov     r4, r6                  /* reloc addr */
 227         add     r0, r0, r4
 228         add     r1, r1, r4
 229         mov     r2, #0x00000000         /* clear                            */
 230
 231 clbss_l:str     r2, [r0]                /* clear loop...                    */
 232         add     r0, r0, #4
 233         cmp     r0, r1
 234         bne     clbss_l
 235 #endif  /* #ifndef CONFIG_PRELOADER */
 236
 237 /*
 238  * We are done. Do not return, instead branch to second part of board
 239  * initialization, now running from RAM.
 240  */
 241 jump_2_ram:
 242         ldr     r0, _board_init_r_ofs
 243         adr     r1, _start
 244         add     lr, r0, r1
 245         add     lr, lr, r9
 246         /* setup parameters for board_init_r */
 247         mov     r0, r5          /* gd_t */
 248         mov     r1, r6          /* dest_addr */
 249         /* jump to it ... */
 250         mov     pc, lr
 251
 252 _board_init_r_ofs:
 253         .word board_init_r - _start
 254
 255 _rel_dyn_start_ofs:
 256         .word __rel_dyn_start - _start
 257 _rel_dyn_end_ofs:
 258         .word __rel_dyn_end - _start
 259 _dynsym_start_ofs:
 260         .word __dynsym_start - _start
 261
 262 /*************************************************************************
 263  *
 264  * CPU_init_critical registers
 265  *
 266  * setup important registers
 267  * setup memory timing
 268  *
 269  *************************************************************************/
 270 cpu_init_crit:
 271         /*
 272          * Invalidate L1 I/D
 273          */
 274         mov     r0, #0                  @ set up for MCR
 275         mcr     p15, 0, r0, c8, c7, 0   @ invalidate TLBs
 276         mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
 277
 278         /*
 279          * disable MMU stuff and caches
 280          */
 281         mrc     p15, 0, r0, c1, c0, 0
 282         bic     r0, r0, #0x00002000     @ clear bits 13 (--V-)
 283         bic     r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)
 284         orr     r0, r0, #0x00000002     @ set bit 1 (--A-) Align
 285         orr     r0, r0, #0x00000800     @ set bit 12 (Z---) BTB
 286         mcr     p15, 0, r0, c1, c0, 0
 287
 288         /*
 289          * Jump to board specific initialization...
 290          * The Mask ROM will have already initialized
 291          * basic memory. Go here to bump up clock rate and handle
 292          * wake up conditions.
 293          */
 294         mov     ip, lr                  @ persevere link reg across call
 295         bl      lowlevel_init           @ go setup pll,mux,memory
 296         mov     lr, ip                  @ restore link
 297         mov     pc, lr                  @ back to my caller
 298 /*
 299  *************************************************************************
 300  *
 301  * Interrupt handling
 302  *
 303  *************************************************************************
 304  */
 305 @
 306 @ IRQ stack frame.
 307 @
 308 #define S_FRAME_SIZE    72
 309
 310 #define S_OLD_R0        68
 311 #define S_PSR           64
 312 #define S_PC            60
 313 #define S_LR            56
 314 #define S_SP            52
 315
 316 #define S_IP            48
 317 #define S_FP            44
 318 #define S_R10           40
 319 #define S_R9            36
 320 #define S_R8            32
 321 #define S_R7            28
 322 #define S_R6            24
 323 #define S_R5            20
 324 #define S_R4            16
 325 #define S_R3            12
 326 #define S_R2            8
 327 #define S_R1            4
 328 #define S_R0            0
 329
 330 #define MODE_SVC 0x13
 331 #define I_BIT    0x80
 332
 333 /*
 334  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 335  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 336  */
 337
 338         .macro  bad_save_user_regs
 339         sub     sp, sp, #S_FRAME_SIZE           @ carve out a frame on current
 340                                                 @ user stack
 341         stmia   sp, {r0 - r12}                  @ Save user registers (now in
 342                                                 @ svc mode) r0-r12
 343         ldr     r2, IRQ_STACK_START_IN          @ set base 2 words into abort
 344                                                 @ stack
 345         ldmia   r2, {r2 - r3}                   @ get values for "aborted" pc
 346                                                 @ and cpsr (into parm regs)
 347         add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
 348
 349         add     r5, sp, #S_SP
 350         mov     r1, lr
 351         stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 352         mov     r0, sp                          @ save current stack into r0
 353                                                 @ (param register)
 354         .endm
 355
 356         .macro  irq_save_user_regs
 357         sub     sp, sp, #S_FRAME_SIZE
 358         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 359         add     r8, sp, #S_PC                   @ !! R8 NEEDS to be saved !!
 360                                                 @ a reserved stack spot would
 361                                                 @ be good.
 362         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 363         str     lr, [r8, #0]                    @ Save calling PC
 364         mrs     r6, spsr
 365         str     r6, [r8, #4]                    @ Save CPSR
 366         str     r0, [r8, #8]                    @ Save OLD_R0
 367         mov     r0, sp
 368         .endm
 369
 370         .macro  irq_restore_user_regs
 371         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 372         mov     r0, r0
 373         ldr     lr, [sp, #S_PC]                 @ Get PC
 374         add     sp, sp, #S_FRAME_SIZE
 375         subs    pc, lr, #4                      @ return & move spsr_svc into
 376                                                 @ cpsr
 377         .endm
 378
 379         .macro get_bad_stack
 380         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack (enter
 381                                                 @ in banked mode)
 382
 383         str     lr, [r13]                       @ save caller lr in position 0
 384                                                 @ of saved stack
 385         mrs     lr, spsr                        @ get the spsr
 386         str     lr, [r13, #4]                   @ save spsr in position 1 of
 387                                                 @ saved stack
 388
 389         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 390         @ msr   spsr_c, r13
 391         msr     spsr, r13                       @ switch modes, make sure
 392                                                 @ moves will execute
 393         mov     lr, pc                          @ capture return pc
 394         movs    pc, lr                          @ jump to next instruction &
 395                                                 @ switch modes.
 396         .endm
 397
 398         .macro get_bad_stack_swi
 399         sub     r13, r13, #4                    @ space on current stack for
 400                                                 @ scratch reg.
 401         str     r0, [r13]                       @ save R0's value.
 402         ldr     r0, IRQ_STACK_START_IN          @ get data regions start
 403                                                 @ spots for abort stack
 404         str     lr, [r0]                        @ save caller lr in position 0
 405                                                 @ of saved stack
 406         mrs     r0, spsr                        @ get the spsr
 407         str     lr, [r0, #4]                    @ save spsr in position 1 of
 408                                                 @ saved stack
 409         ldr     r0, [r13]                       @ restore r0
 410         add     r13, r13, #4                    @ pop stack entry
 411         .endm
 412
 413         .macro get_irq_stack                    @ setup IRQ stack
 414         ldr     sp, IRQ_STACK_START
 415         .endm
 416
 417         .macro get_fiq_stack                    @ setup FIQ stack
 418         ldr     sp, FIQ_STACK_START
 419         .endm
 420
 421 /*
 422  * exception handlers
 423  */
 424         .align  5
 425 undefined_instruction:
 426         get_bad_stack
 427         bad_save_user_regs
 428         bl      do_undefined_instruction
 429
 430         .align  5
 431 software_interrupt:
 432         get_bad_stack_swi
 433         bad_save_user_regs
 434         bl      do_software_interrupt
 435
 436         .align  5
 437 prefetch_abort:
 438         get_bad_stack
 439         bad_save_user_regs
 440         bl      do_prefetch_abort
 441
 442         .align  5
 443 data_abort:
 444         get_bad_stack
 445         bad_save_user_regs
 446         bl      do_data_abort
 447
 448         .align  5
 449 not_used:
 450         get_bad_stack
 451         bad_save_user_regs
 452         bl      do_not_used
 453
 454 #ifdef CONFIG_USE_IRQ
 455
 456         .align  5
 457 irq:
 458         get_irq_stack
 459         irq_save_user_regs
 460         bl      do_irq
 461         irq_restore_user_regs
 462
 463         .align  5
 464 fiq:
 465         get_fiq_stack
 466         /* someone ought to write a more effective fiq_save_user_regs */
 467         irq_save_user_regs
 468         bl      do_fiq
 469         irq_restore_user_regs
 470
 471 #else
 472
 473         .align  5
 474 irq:
 475         get_bad_stack
 476         bad_save_user_regs
 477         bl      do_irq
 478
 479         .align  5
 480 fiq:
 481         get_bad_stack
 482         bad_save_user_regs
 483         bl      do_fiq
 484
 485 #endif