arch/arm/cpu/armv7/start.S

   1 /*
   2  * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
   3  *
   4  * Copyright (c) 2004   Texas Instruments <r-woodruff2@ti.com>
   5  *
   6  * Copyright (c) 2001   Marius Gröger <mag@sysgo.de>
   7  * Copyright (c) 2002   Alex Züpke <azu@sysgo.de>
   8  * Copyright (c) 2002   Gary Jennejohn <garyj@denx.de>
   9  * Copyright (c) 2003   Richard Woodruff <r-woodruff2@ti.com>
  10  * Copyright (c) 2003   Kshitij <kshitij@ti.com>
  11  * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 #include <asm-offsets.h>
  33 #include <config.h>
  34 #include <version.h>
  35
  36 .globl _start
  37 _start: b       reset
  38         ldr     pc, _undefined_instruction
  39         ldr     pc, _software_interrupt
  40         ldr     pc, _prefetch_abort
  41         ldr     pc, _data_abort
  42         ldr     pc, _not_used
  43         ldr     pc, _irq
  44         ldr     pc, _fiq
  45
  46 _undefined_instruction: .word undefined_instruction
  47 _software_interrupt:    .word software_interrupt
  48 _prefetch_abort:        .word prefetch_abort
  49 _data_abort:            .word data_abort
  50 _not_used:              .word not_used
  51 _irq:                   .word irq
  52 _fiq:                   .word fiq
  53 _pad:                   .word 0x12345678 /* now 16*4=64 */
  54 .global _end_vect
  55 _end_vect:
  56
  57         .balignl 16,0xdeadbeef
  58 /*************************************************************************
  59  *
  60  * Startup Code (reset vector)
  61  *
  62  * do important init only if we don't start from memory!
  63  * setup Memory and board specific bits prior to relocation.
  64  * relocate armboot to ram
  65  * setup stack
  66  *
  67  *************************************************************************/
  68
  69 .globl _TEXT_BASE
  70 _TEXT_BASE:
  71         .word   CONFIG_SYS_TEXT_BASE
  72
  73 #ifdef CONFIG_TEGRA2
  74 /*
  75  * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
  76  * U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
  77  * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
  78  * to pick up its reset vector, which points here.
  79  */
  80 .globl _armboot_start
  81 _armboot_start:
  82         .word _start
  83 #endif
  84
  85 /*
  86  * These are defined in the board-specific linker script.
  87  */
  88 .globl _bss_start_ofs
  89 _bss_start_ofs:
  90         .word __bss_start - _start
  91
  92 .globl _bss_end_ofs
  93 _bss_end_ofs:
  94         .word __bss_end__ - _start
  95
  96 .globl _end_ofs
  97 _end_ofs:
  98         .word _end - _start
  99
 100 #ifdef CONFIG_USE_IRQ
 101 /* IRQ stack memory (calculated at run-time) */
 102 .globl IRQ_STACK_START
 103 IRQ_STACK_START:
 104         .word   0x0badc0de
 105
 106 /* IRQ stack memory (calculated at run-time) */
 107 .globl FIQ_STACK_START
 108 FIQ_STACK_START:
 109         .word 0x0badc0de
 110 #endif
 111
 112 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 113 .globl IRQ_STACK_START_IN
 114 IRQ_STACK_START_IN:
 115         .word   0x0badc0de
 116
 117 /*
 118  * the actual reset code
 119  */
 120
 121 reset:
 122         /*
 123          * set the cpu to SVC32 mode
 124          */
 125         mrs     r0, cpsr
 126         bic     r0, r0, #0x1f
 127         orr     r0, r0, #0xd3
 128         msr     cpsr,r0
 129
 130 #if defined(CONFIG_OMAP34XX)
 131         /* Copy vectors to mask ROM indirect addr */
 132         adr     r0, _start              @ r0 <- current position of code
 133         add     r0, r0, #4              @ skip reset vector
 134         mov     r2, #64                 @ r2 <- size to copy
 135         add     r2, r0, r2              @ r2 <- source end address
 136         mov     r1, #SRAM_OFFSET0       @ build vect addr
 137         mov     r3, #SRAM_OFFSET1
 138         add     r1, r1, r3
 139         mov     r3, #SRAM_OFFSET2
 140         add     r1, r1, r3
 141 next:
 142         ldmia   r0!, {r3 - r10}         @ copy from source address [r0]
 143         stmia   r1!, {r3 - r10}         @ copy to   target address [r1]
 144         cmp     r0, r2                  @ until source end address [r2]
 145         bne     next                    @ loop until equal */
 146 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
 147         /* No need to copy/exec the clock code - DPLL adjust already done
 148          * in NAND/oneNAND Boot.
 149          */
 150         bl      cpy_clk_code            @ put dpll adjust code behind vectors
 151 #endif /* NAND Boot */
 152 #endif
 153         /* the mask ROM code should have PLL and others stable */
 154 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 155         bl      cpu_init_crit
 156 #endif
 157
 158 /* Set stackpointer in internal RAM to call board_init_f */
 159 call_board_init_f:
 160         ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 161         bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
 162         ldr     r0,=0x00000000
 163         bl      board_init_f
 164
 165 /*------------------------------------------------------------------------------*/
 166
 167 /*
 168  * void relocate_code (addr_sp, gd, addr_moni)
 169  *
 170  * This "function" does not return, instead it continues in RAM
 171  * after relocating the monitor code.
 172  *
 173  */
 174         .globl  relocate_code
 175 relocate_code:
 176         mov     r4, r0  /* save addr_sp */
 177         mov     r5, r1  /* save addr of gd */
 178         mov     r6, r2  /* save addr of destination */
 179
 180         /* Set up the stack                                                 */
 181 stack_setup:
 182         mov     sp, r4
 183
 184         adr     r0, _start
 185 #ifndef CONFIG_PRELOADER
 186         cmp     r0, r6
 187         beq     clear_bss               /* skip relocation */
 188 #endif
 189         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 190         ldr     r3, _bss_start_ofs
 191         add     r2, r0, r3              /* r2 <- source end address         */
 192
 193 copy_loop:
 194         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 195         stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 196         cmp     r0, r2                  /* until source end address [r2]    */
 197         blo     copy_loop
 198
 199 #ifndef CONFIG_PRELOADER
 200         /*
 201          * fix .rel.dyn relocations
 202          */
 203         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 204         sub     r9, r6, r0              /* r9 <- relocation offset */
 205         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 206         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 207         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 208         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 209         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 210         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 211 fixloop:
 212         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 213         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 214         ldr     r1, [r2, #4]
 215         and     r7, r1, #0xff
 216         cmp     r7, #23                 /* relative fixup? */
 217         beq     fixrel
 218         cmp     r7, #2                  /* absolute fixup? */
 219         beq     fixabs
 220         /* ignore unknown type of fixup */
 221         b       fixnext
 222 fixabs:
 223         /* absolute fix: set location to (offset) symbol value */
 224         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 225         add     r1, r10, r1             /* r1 <- address of symbol in table */
 226         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 227         add     r1, r1, r9              /* r1 <- relocated sym addr */
 228         b       fixnext
 229 fixrel:
 230         /* relative fix: increase location by offset */
 231         ldr     r1, [r0]
 232         add     r1, r1, r9
 233 fixnext:
 234         str     r1, [r0]
 235         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 236         cmp     r2, r3
 237         blo     fixloop
 238
 239 clear_bss:
 240         ldr     r0, _bss_start_ofs
 241         ldr     r1, _bss_end_ofs
 242         mov     r4, r6                  /* reloc addr */
 243         add     r0, r0, r4
 244         add     r1, r1, r4
 245         mov     r2, #0x00000000         /* clear                            */
 246
 247 clbss_l:str     r2, [r0]                /* clear loop...                    */
 248         add     r0, r0, #4
 249         cmp     r0, r1
 250         bne     clbss_l
 251 #endif  /* #ifndef CONFIG_PRELOADER */
 252
 253 /*
 254  * We are done. Do not return, instead branch to second part of board
 255  * initialization, now running from RAM.
 256  */
 257 jump_2_ram:
 258         ldr     r0, _board_init_r_ofs
 259         adr     r1, _start
 260         add     lr, r0, r1
 261         add     lr, lr, r9
 262         /* setup parameters for board_init_r */
 263         mov     r0, r5          /* gd_t */
 264         mov     r1, r6          /* dest_addr */
 265         /* jump to it ... */
 266         mov     pc, lr
 267
 268 _board_init_r_ofs:
 269         .word board_init_r - _start
 270
 271 _rel_dyn_start_ofs:
 272         .word __rel_dyn_start - _start
 273 _rel_dyn_end_ofs:
 274         .word __rel_dyn_end - _start
 275 _dynsym_start_ofs:
 276         .word __dynsym_start - _start
 277
 278 /*************************************************************************
 279  *
 280  * CPU_init_critical registers
 281  *
 282  * setup important registers
 283  * setup memory timing
 284  *
 285  *************************************************************************/
 286 cpu_init_crit:
 287         /*
 288          * Invalidate L1 I/D
 289          */
 290         mov     r0, #0                  @ set up for MCR
 291         mcr     p15, 0, r0, c8, c7, 0   @ invalidate TLBs
 292         mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
 293
 294         /*
 295          * disable MMU stuff and caches
 296          */
 297         mrc     p15, 0, r0, c1, c0, 0
 298         bic     r0, r0, #0x00002000     @ clear bits 13 (--V-)
 299         bic     r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)
 300         orr     r0, r0, #0x00000002     @ set bit 1 (--A-) Align
 301         orr     r0, r0, #0x00000800     @ set bit 12 (Z---) BTB
 302         mcr     p15, 0, r0, c1, c0, 0
 303
 304         /*
 305          * Jump to board specific initialization...
 306          * The Mask ROM will have already initialized
 307          * basic memory. Go here to bump up clock rate and handle
 308          * wake up conditions.
 309          */
 310         mov     ip, lr                  @ persevere link reg across call
 311         bl      lowlevel_init           @ go setup pll,mux,memory
 312         mov     lr, ip                  @ restore link
 313         mov     pc, lr                  @ back to my caller
 314 /*
 315  *************************************************************************
 316  *
 317  * Interrupt handling
 318  *
 319  *************************************************************************
 320  */
 321 @
 322 @ IRQ stack frame.
 323 @
 324 #define S_FRAME_SIZE    72
 325
 326 #define S_OLD_R0        68
 327 #define S_PSR           64
 328 #define S_PC            60
 329 #define S_LR            56
 330 #define S_SP            52
 331
 332 #define S_IP            48
 333 #define S_FP            44
 334 #define S_R10           40
 335 #define S_R9            36
 336 #define S_R8            32
 337 #define S_R7            28
 338 #define S_R6            24
 339 #define S_R5            20
 340 #define S_R4            16
 341 #define S_R3            12
 342 #define S_R2            8
 343 #define S_R1            4
 344 #define S_R0            0
 345
 346 #define MODE_SVC 0x13
 347 #define I_BIT    0x80
 348
 349 /*
 350  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 351  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 352  */
 353
 354         .macro  bad_save_user_regs
 355         sub     sp, sp, #S_FRAME_SIZE           @ carve out a frame on current
 356                                                 @ user stack
 357         stmia   sp, {r0 - r12}                  @ Save user registers (now in
 358                                                 @ svc mode) r0-r12
 359         ldr     r2, IRQ_STACK_START_IN          @ set base 2 words into abort
 360                                                 @ stack
 361         ldmia   r2, {r2 - r3}                   @ get values for "aborted" pc
 362                                                 @ and cpsr (into parm regs)
 363         add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
 364
 365         add     r5, sp, #S_SP
 366         mov     r1, lr
 367         stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 368         mov     r0, sp                          @ save current stack into r0
 369                                                 @ (param register)
 370         .endm
 371
 372         .macro  irq_save_user_regs
 373         sub     sp, sp, #S_FRAME_SIZE
 374         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 375         add     r8, sp, #S_PC                   @ !! R8 NEEDS to be saved !!
 376                                                 @ a reserved stack spot would
 377                                                 @ be good.
 378         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 379         str     lr, [r8, #0]                    @ Save calling PC
 380         mrs     r6, spsr
 381         str     r6, [r8, #4]                    @ Save CPSR
 382         str     r0, [r8, #8]                    @ Save OLD_R0
 383         mov     r0, sp
 384         .endm
 385
 386         .macro  irq_restore_user_regs
 387         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 388         mov     r0, r0
 389         ldr     lr, [sp, #S_PC]                 @ Get PC
 390         add     sp, sp, #S_FRAME_SIZE
 391         subs    pc, lr, #4                      @ return & move spsr_svc into
 392                                                 @ cpsr
 393         .endm
 394
 395         .macro get_bad_stack
 396         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack (enter
 397                                                 @ in banked mode)
 398
 399         str     lr, [r13]                       @ save caller lr in position 0
 400                                                 @ of saved stack
 401         mrs     lr, spsr                        @ get the spsr
 402         str     lr, [r13, #4]                   @ save spsr in position 1 of
 403                                                 @ saved stack
 404
 405         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 406         @ msr   spsr_c, r13
 407         msr     spsr, r13                       @ switch modes, make sure
 408                                                 @ moves will execute
 409         mov     lr, pc                          @ capture return pc
 410         movs    pc, lr                          @ jump to next instruction &
 411                                                 @ switch modes.
 412         .endm
 413
 414         .macro get_bad_stack_swi
 415         sub     r13, r13, #4                    @ space on current stack for
 416                                                 @ scratch reg.
 417         str     r0, [r13]                       @ save R0's value.
 418         ldr     r0, IRQ_STACK_START_IN          @ get data regions start
 419                                                 @ spots for abort stack
 420         str     lr, [r0]                        @ save caller lr in position 0
 421                                                 @ of saved stack
 422         mrs     r0, spsr                        @ get the spsr
 423         str     lr, [r0, #4]                    @ save spsr in position 1 of
 424                                                 @ saved stack
 425         ldr     r0, [r13]                       @ restore r0
 426         add     r13, r13, #4                    @ pop stack entry
 427         .endm
 428
 429         .macro get_irq_stack                    @ setup IRQ stack
 430         ldr     sp, IRQ_STACK_START
 431         .endm
 432
 433         .macro get_fiq_stack                    @ setup FIQ stack
 434         ldr     sp, FIQ_STACK_START
 435         .endm
 436
 437 /*
 438  * exception handlers
 439  */
 440         .align  5
 441 undefined_instruction:
 442         get_bad_stack
 443         bad_save_user_regs
 444         bl      do_undefined_instruction
 445
 446         .align  5
 447 software_interrupt:
 448         get_bad_stack_swi
 449         bad_save_user_regs
 450         bl      do_software_interrupt
 451
 452         .align  5
 453 prefetch_abort:
 454         get_bad_stack
 455         bad_save_user_regs
 456         bl      do_prefetch_abort
 457
 458         .align  5
 459 data_abort:
 460         get_bad_stack
 461         bad_save_user_regs
 462         bl      do_data_abort
 463
 464         .align  5
 465 not_used:
 466         get_bad_stack
 467         bad_save_user_regs
 468         bl      do_not_used
 469
 470 #ifdef CONFIG_USE_IRQ
 471
 472         .align  5
 473 irq:
 474         get_irq_stack
 475         irq_save_user_regs
 476         bl      do_irq
 477         irq_restore_user_regs
 478
 479         .align  5
 480 fiq:
 481         get_fiq_stack
 482         /* someone ought to write a more effective fiq_save_user_regs */
 483         irq_save_user_regs
 484         bl      do_fiq
 485         irq_restore_user_regs
 486
 487 #else
 488
 489         .align  5
 490 irq:
 491         get_bad_stack
 492         bad_save_user_regs
 493         bl      do_irq
 494
 495         .align  5
 496 fiq:
 497         get_bad_stack
 498         bad_save_user_regs
 499         bl      do_fiq
 500
 501 #endif