arch/arm/cpu/armv7/sunxi/board.c

   1 /*
   2  * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
   3  *
   4  * (C) Copyright 2007-2011
   5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   6  * Tom Cubie <tangliang@allwinnertech.com>
   7  *
   8  * Some init for sunxi platform.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <mmc.h>
  15 #include <i2c.h>
  16 #include <serial.h>
  17 #ifdef CONFIG_SPL_BUILD
  18 #include <spl.h>
  19 #endif
  20 #include <asm/gpio.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/clock.h>
  23 #include <asm/arch/gpio.h>
  24 #include <asm/arch/spl.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm/arch/timer.h>
  27 #include <asm/arch/tzpc.h>
  28 #include <asm/arch/mmc.h>
  29
  30 #include <linux/compiler.h>
  31
  32 struct fel_stash {
  33         uint32_t sp;
  34         uint32_t lr;
  35         uint32_t cpsr;
  36         uint32_t sctlr;
  37         uint32_t vbar;
  38         uint32_t cr;
  39 };
  40
  41 struct fel_stash fel_stash __attribute__((section(".data")));
  42
  43 static int gpio_init(void)
  44 {
  45 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
  46 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  47         /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
  48         sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
  49         sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
  50 #endif
  51 #if defined(CONFIG_MACH_SUN8I)
  52         sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
  53         sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
  54 #else
  55         sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
  56         sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
  57 #endif
  58         sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
  59 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
  60         sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
  61         sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
  62         sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
  63 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
  64         sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
  65         sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
  66         sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
  67 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
  68         sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
  69         sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
  70         sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
  71 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
  72         sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
  73         sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
  74         sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
  75 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
  76         sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
  77         sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
  78         sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
  79 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
  80         sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
  81         sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
  82         sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
  83 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
  84         sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
  85         sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
  86         sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
  87 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
  88         sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
  89         sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
  90         sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
  91 #else
  92 #error Unsupported console port number. Please fix pin mux settings in board.c
  93 #endif
  94
  95         return 0;
  96 }
  97
  98 int spl_board_load_image(void)
  99 {
 100         debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
 101         return_to_fel(fel_stash.sp, fel_stash.lr);
 102
 103         return 0;
 104 }
 105
 106 void s_init(void)
 107 {
 108 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
 109         /* Magic (undocmented) value taken from boot0, without this DRAM
 110          * access gets messed up (seems cache related) */
 111         setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
 112 #endif
 113 #if defined CONFIG_MACH_SUN6I || \
 114     defined CONFIG_MACH_SUN7I || \
 115     defined CONFIG_MACH_SUN8I
 116         /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
 117         asm volatile(
 118                 "mrc p15, 0, r0, c1, c0, 1\n"
 119                 "orr r0, r0, #1 << 6\n"
 120                 "mcr p15, 0, r0, c1, c0, 1\n");
 121 #endif
 122 #if defined CONFIG_MACH_SUN6I
 123         /* Enable non-secure access to the RTC */
 124         tzpc_init();
 125 #endif
 126
 127         clock_init();
 128         timer_init();
 129         gpio_init();
 130         i2c_init_board();
 131 }
 132
 133 #ifdef CONFIG_SPL_BUILD
 134 DECLARE_GLOBAL_DATA_PTR;
 135
 136 /* The sunxi internal brom will try to loader external bootloader
 137  * from mmc0, nand flash, mmc2.
 138  */
 139 u32 spl_boot_device(void)
 140 {
 141         __maybe_unused struct mmc *mmc0, *mmc1;
 142         /*
 143          * When booting from the SD card or NAND memory, the "eGON.BT0"
 144          * signature is expected to be found in memory at the address 0x0004
 145          * (see the "mksunxiboot" tool, which generates this header).
 146          *
 147          * When booting in the FEL mode over USB, this signature is patched in
 148          * memory and replaced with something else by the 'fel' tool. This other
 149          * signature is selected in such a way, that it can't be present in a
 150          * valid bootable SD card image (because the BROM would refuse to
 151          * execute the SPL in this case).
 152          *
 153          * This checks for the signature and if it is not found returns to
 154          * the FEL code in the BROM to wait and receive the main u-boot
 155          * binary over USB. If it is found, it determines where SPL was
 156          * read from.
 157          */
 158         if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
 159                 return BOOT_DEVICE_BOARD;
 160
 161         /* The BROM will try to boot from mmc0 first, so try that first. */
 162 #ifdef CONFIG_MMC
 163         mmc_initialize(gd->bd);
 164         mmc0 = find_mmc_device(0);
 165         if (sunxi_mmc_has_egon_boot_signature(mmc0))
 166                 return BOOT_DEVICE_MMC1;
 167 #endif
 168
 169         /* Fallback to booting NAND if enabled. */
 170         if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
 171                 return BOOT_DEVICE_NAND;
 172
 173 #ifdef CONFIG_MMC
 174         if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
 175                 mmc1 = find_mmc_device(1);
 176                 if (sunxi_mmc_has_egon_boot_signature(mmc1))
 177                         return BOOT_DEVICE_MMC2;
 178         }
 179 #endif
 180
 181         panic("Could not determine boot source\n");
 182         return -1;              /* Never reached */
 183 }
 184
 185 /* No confirmation data available in SPL yet. Hardcode bootmode */
 186 u32 spl_boot_mode(void)
 187 {
 188         return MMCSD_MODE_RAW;
 189 }
 190
 191 void board_init_f(ulong dummy)
 192 {
 193         spl_init();
 194         preloader_console_init();
 195
 196 #ifdef CONFIG_SPL_I2C_SUPPORT
 197         /* Needed early by sunxi_board_init if PMU is enabled */
 198         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 199 #endif
 200         sunxi_board_init();
 201 }
 202 #endif
 203
 204 void reset_cpu(ulong addr)
 205 {
 206 #ifdef CONFIG_SUNXI_GEN_SUN4I
 207         static const struct sunxi_wdog *wdog =
 208                  &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 209
 210         /* Set the watchdog for its shortest interval (.5s) and wait */
 211         writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
 212         writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
 213
 214         while (1) {
 215                 /* sun5i sometimes gets stuck without this */
 216                 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
 217         }
 218 #endif
 219 #ifdef CONFIG_SUNXI_GEN_SUN6I
 220         static const struct sunxi_wdog *wdog =
 221                  ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 222
 223         /* Set the watchdog for its shortest interval (.5s) and wait */
 224         writel(WDT_CFG_RESET, &wdog->cfg);
 225         writel(WDT_MODE_EN, &wdog->mode);
 226         writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
 227         while (1) { }
 228 #endif
 229 }
 230
 231 #ifndef CONFIG_SYS_DCACHE_OFF
 232 void enable_caches(void)
 233 {
 234         /* Enable D-cache. I-cache is already enabled in start.S */
 235         dcache_enable();
 236 }
 237 #endif
 238
 239 #ifdef CONFIG_CMD_NET
 240 /*
 241  * Initializes on-chip ethernet controllers.
 242  * to override, implement board_eth_init()
 243  */
 244 int cpu_eth_init(bd_t *bis)
 245 {
 246         __maybe_unused int rc;
 247
 248 #ifdef CONFIG_MACPWR
 249         gpio_request(CONFIG_MACPWR, "macpwr");
 250         gpio_direction_output(CONFIG_MACPWR, 1);
 251         mdelay(200);
 252 #endif
 253
 254 #ifdef CONFIG_SUNXI_GMAC
 255         rc = sunxi_gmac_initialize(bis);
 256         if (rc < 0) {
 257                 printf("sunxi: failed to initialize gmac\n");
 258                 return rc;
 259         }
 260 #endif
 261
 262         return 0;
 263 }
 264 #endif