arch/arm/cpu/armv7/sunxi/clock_sun6i.c

   1 /*
   2  * sun6i specific clock code
   3  *
   4  * (C) Copyright 2007-2012
   5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   6  * Tom Cubie <tangliang@allwinnertech.com>
   7  *
   8  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/prcm.h>
  17 #include <asm/arch/sys_proto.h>
  18
  19 #ifdef CONFIG_SPL_BUILD
  20 void clock_init_safe(void)
  21 {
  22         struct sunxi_ccm_reg * const ccm =
  23                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  24         struct sunxi_prcm_reg * const prcm =
  25                 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
  26
  27         /* Set PLL ldo voltage without this PLL6 does not work properly */
  28         clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
  29                         PRCM_PLL_CTRL_LDO_KEY);
  30         clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
  31                 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
  32                 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
  33         clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
  34
  35         clock_set_pll1(408000000);
  36
  37         writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
  38
  39         writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
  40
  41         writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
  42         writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
  43 }
  44 #endif
  45
  46 void clock_init_uart(void)
  47 {
  48 #if CONFIG_CONS_INDEX < 5
  49         struct sunxi_ccm_reg *const ccm =
  50                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  51
  52         /* uart clock source is apb2 */
  53         writel(APB2_CLK_SRC_OSC24M|
  54                APB2_CLK_RATE_N_1|
  55                APB2_CLK_RATE_M(1),
  56                &ccm->apb2_div);
  57
  58         /* open the clock for uart */
  59         setbits_le32(&ccm->apb2_gate,
  60                      CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
  61                                        CONFIG_CONS_INDEX - 1));
  62
  63         /* deassert uart reset */
  64         setbits_le32(&ccm->apb2_reset_cfg,
  65                      1 << (APB2_RESET_UART_SHIFT +
  66                            CONFIG_CONS_INDEX - 1));
  67 #else
  68         /* enable R_PIO and R_UART clocks, and de-assert resets */
  69         prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
  70 #endif
  71 }
  72
  73 int clock_twi_onoff(int port, int state)
  74 {
  75         struct sunxi_ccm_reg *const ccm =
  76                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  77
  78         if (port > 3)
  79                 return -1;
  80
  81         /* set the apb clock gate for twi */
  82         if (state)
  83                 setbits_le32(&ccm->apb2_gate,
  84                              CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
  85         else
  86                 clrbits_le32(&ccm->apb2_gate,
  87                              CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
  88
  89         return 0;
  90 }
  91
  92 #ifdef CONFIG_SPL_BUILD
  93 void clock_set_pll1(unsigned int clk)
  94 {
  95         struct sunxi_ccm_reg * const ccm =
  96                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  97         const int p = 0;
  98         int k = 1;
  99         int m = 1;
 100
 101         if (clk > 1152000000) {
 102                 k = 2;
 103         } else if (clk > 768000000) {
 104                 k = 3;
 105                 m = 2;
 106         }
 107
 108         /* Switch to 24MHz clock while changing PLL1 */
 109         writel(AXI_DIV_3 << AXI_DIV_SHIFT |
 110                ATB_DIV_2 << ATB_DIV_SHIFT |
 111                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 112                &ccm->cpu_axi_cfg);
 113
 114         /*
 115          * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m   (p is ignored)
 116          * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
 117          */
 118         writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
 119                CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
 120                CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
 121         sdelay(200);
 122
 123         /* Switch CPU to PLL1 */
 124         writel(AXI_DIV_3 << AXI_DIV_SHIFT |
 125                ATB_DIV_2 << ATB_DIV_SHIFT |
 126                CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 127                &ccm->cpu_axi_cfg);
 128 }
 129 #endif
 130
 131 void clock_set_pll3(unsigned int clk)
 132 {
 133         struct sunxi_ccm_reg * const ccm =
 134                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 135         const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
 136
 137         if (clk == 0) {
 138                 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
 139                 return;
 140         }
 141
 142         /* PLL3 rate = 24000000 * n / m */
 143         writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
 144                CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
 145                &ccm->pll3_cfg);
 146 }
 147
 148 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
 149 {
 150         struct sunxi_ccm_reg * const ccm =
 151                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 152         const int max_n = 32;
 153         int k = 1, m = 2;
 154
 155         if (sigma_delta_enable)
 156                 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
 157
 158         /* PLL5 rate = 24000000 * n * k / m */
 159         if (clk > 24000000 * k * max_n / m) {
 160                 m = 1;
 161                 if (clk > 24000000 * k * max_n / m)
 162                         k = 2;
 163         }
 164         writel(CCM_PLL5_CTRL_EN |
 165                (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
 166                CCM_PLL5_CTRL_UPD |
 167                CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
 168                CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
 169
 170         udelay(5500);
 171 }
 172
 173 #ifdef CONFIG_MACH_SUN6I
 174 void clock_set_mipi_pll(unsigned int clk)
 175 {
 176         struct sunxi_ccm_reg * const ccm =
 177                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 178         unsigned int k, m, n, value, diff;
 179         unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
 180         unsigned int src = clock_get_pll3();
 181
 182         /* All calculations are in KHz to avoid overflows */
 183         clk /= 1000;
 184         src /= 1000;
 185
 186         /* Pick the closest lower clock */
 187         for (k = 1; k <= 4; k++) {
 188                 for (m = 1; m <= 16; m++) {
 189                         for (n = 1; n <= 16; n++) {
 190                                 value = src * n * k / m;
 191                                 if (value > clk)
 192                                         continue;
 193
 194                                 diff = clk - value;
 195                                 if (diff < best_diff) {
 196                                         best_diff = diff;
 197                                         best_k = k;
 198                                         best_m = m;
 199                                         best_n = n;
 200                                 }
 201                                 if (diff == 0)
 202                                         goto done;
 203                         }
 204                 }
 205         }
 206
 207 done:
 208         writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
 209                CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
 210                CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
 211 }
 212 #endif
 213
 214 #ifdef CONFIG_MACH_SUN8I_A33
 215 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
 216 {
 217         struct sunxi_ccm_reg * const ccm =
 218                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 219
 220         if (sigma_delta_enable)
 221                 writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
 222
 223         writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
 224                (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
 225                CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
 226
 227         while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
 228                 ;
 229 }
 230 #endif
 231
 232 unsigned int clock_get_pll3(void)
 233 {
 234         struct sunxi_ccm_reg *const ccm =
 235                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 236         uint32_t rval = readl(&ccm->pll3_cfg);
 237         int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
 238         int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
 239
 240         /* Multiply by 1000 after dividing by m to avoid integer overflows */
 241         return (24000 * n / m) * 1000;
 242 }
 243
 244 unsigned int clock_get_pll6(void)
 245 {
 246         struct sunxi_ccm_reg *const ccm =
 247                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 248         uint32_t rval = readl(&ccm->pll6_cfg);
 249         int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
 250         int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
 251         return 24000000 * n * k / 2;
 252 }
 253
 254 unsigned int clock_get_mipi_pll(void)
 255 {
 256         struct sunxi_ccm_reg *const ccm =
 257                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 258         uint32_t rval = readl(&ccm->mipi_pll_cfg);
 259         unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
 260         unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
 261         unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
 262         unsigned int src = clock_get_pll3();
 263
 264         /* Multiply by 1000 after dividing by m to avoid integer overflows */
 265         return ((src / 1000) * n * k / m) * 1000;
 266 }
 267
 268 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
 269 {
 270         int pll = clock_get_pll6() * 2;
 271         int div = 1;
 272
 273         while ((pll / div) > hz)
 274                 div++;
 275
 276         writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
 277                clk_cfg);
 278 }