arch/arm/cpu/armv7/sunxi/psci.S

   1 /*
   2  * Copyright (C) 2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Based on code by Carl van Schaik <carl@ok-labs.com>.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <config.h>
  21 #include <asm/gic.h>
  22 #include <asm/macro.h>
  23 #include <asm/psci.h>
  24 #include <asm/arch/cpu.h>
  25
  26 /*
  27  * Memory layout:
  28  *
  29  * SECURE_RAM to text_end :
  30  *      ._secure_text section
  31  * text_end to ALIGN_PAGE(text_end):
  32  *      nothing
  33  * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
  34  *      1kB of stack per CPU (4 CPUs max).
  35  */
  36
  37         .pushsection ._secure.text, "ax"
  38
  39         .arch_extension sec
  40
  41 #define ONE_MS                  (CONFIG_TIMER_CLK_FREQ / 1000)
  42 #define TEN_MS                  (10 * ONE_MS)
  43 #define GICD_BASE               0x1c81000
  44 #define GICC_BASE               0x1c82000
  45
  46 .macro  timer_wait      reg, ticks
  47         @ Program CNTP_TVAL
  48         movw    \reg, #(\ticks & 0xffff)
  49         movt    \reg, #(\ticks >> 16)
  50         mcr     p15, 0, \reg, c14, c2, 0
  51         isb
  52         @ Enable physical timer, mask interrupt
  53         mov     \reg, #3
  54         mcr     p15, 0, \reg, c14, c2, 1
  55         @ Poll physical timer until ISTATUS is on
  56 1:      isb
  57         mrc     p15, 0, \reg, c14, c2, 1
  58         ands    \reg, \reg, #4
  59         bne     1b
  60         @ Disable timer
  61         mov     \reg, #0
  62         mcr     p15, 0, \reg, c14, c2, 1
  63         isb
  64 .endm
  65
  66 .globl  psci_fiq_enter
  67 psci_fiq_enter:
  68         push    {r0-r12}
  69
  70         @ Switch to secure
  71         mrc     p15, 0, r7, c1, c1, 0
  72         bic     r8, r7, #1
  73         mcr     p15, 0, r8, c1, c1, 0
  74         isb
  75
  76         @ Validate reason based on IAR and acknowledge
  77         movw    r8, #(GICC_BASE & 0xffff)
  78         movt    r8, #(GICC_BASE >> 16)
  79         ldr     r9, [r8, #GICC_IAR]
  80         movw    r10, #0x3ff
  81         movt    r10, #0
  82         cmp     r9, r10                 @ skip spurious interrupt 1023
  83         beq     out
  84         movw    r10, #0x3fe             @ ...and 1022
  85         cmp     r9, r10
  86         beq     out
  87         str     r9, [r8, #GICC_EOIR]    @ acknowledge the interrupt
  88         dsb
  89
  90         @ Compute CPU number
  91         lsr     r9, r9, #10
  92         and     r9, r9, #0xf
  93
  94         movw    r8, #(SUN7I_CPUCFG_BASE & 0xffff)
  95         movt    r8, #(SUN7I_CPUCFG_BASE >> 16)
  96
  97         @ Wait for the core to enter WFI
  98         lsl     r11, r9, #6             @ x64
  99         add     r11, r11, r8
 100
 101 1:      ldr     r10, [r11, #0x48]
 102         tst     r10, #(1 << 2)
 103         bne     2f
 104         timer_wait r10, ONE_MS
 105         b       1b
 106
 107         @ Reset CPU
 108 2:      mov     r10, #0
 109         str     r10, [r11, #0x40]
 110
 111         @ Lock CPU
 112         mov     r10, #1
 113         lsl     r9, r10, r9             @ r9 is now CPU mask
 114         ldr     r10, [r8, #0x1e4]
 115         bic     r10, r10, r9
 116         str     r10, [r8, #0x1e4]
 117
 118         @ Set power gating
 119         ldr     r10, [r8, #0x1b4]
 120         orr     r10, r10, #1
 121         str     r10, [r8, #0x1b4]
 122         timer_wait r10, ONE_MS
 123
 124         @ Activate power clamp
 125         mov     r10, #1
 126 1:      str     r10, [r8, #0x1b0]
 127         lsl     r10, r10, #1
 128         orr     r10, r10, #1
 129         tst     r10, #0x100
 130         beq     1b
 131
 132         @ Restore security level
 133 out:    mcr     p15, 0, r7, c1, c1, 0
 134
 135         pop     {r0-r12}
 136         subs    pc, lr, #4
 137
 138         @ r1 = target CPU
 139         @ r2 = target PC
 140 .globl  psci_cpu_on
 141 psci_cpu_on:
 142         push    {lr}
 143
 144         mov     r0, r1
 145         bl      psci_get_cpu_stack_top  @ get stack top of target CPU
 146         str     r2, [r0]                @ store target PC at stack top
 147         dsb
 148
 149         movw    r0, #(SUN7I_CPUCFG_BASE & 0xffff)
 150         movt    r0, #(SUN7I_CPUCFG_BASE >> 16)
 151
 152         @ CPU mask
 153         and     r1, r1, #3      @ only care about first cluster
 154         mov     r4, #1
 155         lsl     r4, r4, r1
 156
 157         ldr     r6, =psci_cpu_entry
 158         str     r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
 159
 160         @ Assert reset on target CPU
 161         mov     r6, #0
 162         lsl     r5, r1, #6      @ 64 bytes per CPU
 163         add     r5, r5, #0x40   @ Offset from base
 164         add     r5, r5, r0      @ CPU control block
 165         str     r6, [r5]        @ Reset CPU
 166
 167         @ l1 invalidate
 168         ldr     r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
 169         bic     r6, r6, r4
 170         str     r6, [r0, #0x184]
 171
 172         @ Lock CPU (Disable external debug access)
 173         ldr     r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
 174         bic     r6, r6, r4
 175         str     r6, [r0, #0x1e4]
 176
 177         @ Release power clamp
 178         movw    r6, #0x1ff
 179         movt    r6, #0
 180 1:      lsrs    r6, r6, #1
 181         str     r6, [r0, #0x1b0] @ CPU1_PWR_CLAMP
 182         bne     1b
 183
 184         timer_wait r1, TEN_MS
 185
 186         @ Clear power gating
 187         ldr     r6, [r0, #0x1b4] @ CPU1_PWROFF_REG
 188         bic     r6, r6, #1
 189         str     r6, [r0, #0x1b4]
 190
 191         @ Deassert reset on target CPU
 192         mov     r6, #3
 193         str     r6, [r5]
 194
 195         @ Unlock CPU (Enable external debug access)
 196         ldr     r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
 197         orr     r6, r6, r4
 198         str     r6, [r0, #0x1e4]
 199
 200         mov     r0, #ARM_PSCI_RET_SUCCESS       @ Return PSCI_RET_SUCCESS
 201         pop     {pc}
 202
 203 .globl  psci_cpu_off
 204 psci_cpu_off:
 205         bl      psci_cpu_off_common
 206
 207         @ Ask CPU0 to pull the rug...
 208         movw    r0, #(GICD_BASE & 0xffff)
 209         movt    r0, #(GICD_BASE >> 16)
 210         movw    r1, #15                         @ SGI15
 211         movt    r1, #1                          @ Target is CPU0
 212         str     r1, [r0, #GICD_SGIR]
 213         dsb
 214
 215 1:      wfi
 216         b       1b
 217
 218 .globl  psci_arch_init
 219 psci_arch_init:
 220         mov     r6, lr
 221
 222         movw    r4, #(GICD_BASE & 0xffff)
 223         movt    r4, #(GICD_BASE >> 16)
 224
 225         ldr     r5, [r4, #GICD_IGROUPRn]
 226         bic     r5, r5, #(1 << 15)      @ SGI15 as Group-0
 227         str     r5, [r4, #GICD_IGROUPRn]
 228
 229         mov     r5, #0                  @ Set SGI15 priority to 0
 230         strb    r5, [r4, #(GICD_IPRIORITYRn + 15)]
 231
 232         add     r4, r4, #0x1000         @ GICC address
 233
 234         mov     r5, #0xff
 235         str     r5, [r4, #GICC_PMR]     @ Be cool with non-secure
 236
 237         ldr     r5, [r4, #GICC_CTLR]
 238         orr     r5, r5, #(1 << 3)       @ Switch FIQEn on
 239         str     r5, [r4, #GICC_CTLR]
 240
 241         mrc     p15, 0, r5, c1, c1, 0   @ Read SCR
 242         orr     r5, r5, #4              @ Enable FIQ in monitor mode
 243         bic     r5, r5, #1              @ Secure mode
 244         mcr     p15, 0, r5, c1, c1, 0   @ Write SCR
 245         isb
 246
 247         bl      psci_get_cpu_id         @ CPU ID => r0
 248         bl      psci_get_cpu_stack_top  @ stack top => r0
 249         mov     sp, r0
 250
 251         bx      r6
 252
 253         .globl psci_text_end
 254 psci_text_end:
 255         .popsection