arch/arm/cpu/armv7/sunxi/psci_sun6i.S

   1 /*
   2  * Copyright (C) 2015 - Chen-Yu Tsai
   3  * Author: Chen-Yu Tsai <wens@csie.org>
   4  *
   5  * Based on psci_sun7i.S by Marc Zyngier <marc.zyngier@arm.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <config.h>
  21
  22 #include <asm/arch-armv7/generictimer.h>
  23 #include <asm/gic.h>
  24 #include <asm/macro.h>
  25 #include <asm/psci.h>
  26 #include <asm/arch/cpu.h>
  27
  28 /*
  29  * Memory layout:
  30  *
  31  * SECURE_RAM to text_end :
  32  *      ._secure_text section
  33  * text_end to ALIGN_PAGE(text_end):
  34  *      nothing
  35  * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
  36  *      1kB of stack per CPU (4 CPUs max).
  37  */
  38
  39         .pushsection ._secure.text, "ax"
  40
  41         .arch_extension sec
  42
  43 #define ONE_MS                  (CONFIG_TIMER_CLK_FREQ / 1000)
  44 #define TEN_MS                  (10 * ONE_MS)
  45 #define GICD_BASE               0x1c81000
  46 #define GICC_BASE               0x1c82000
  47
  48 .globl  psci_fiq_enter
  49 psci_fiq_enter:
  50         push    {r0-r12}
  51
  52         @ Switch to secure
  53         mrc     p15, 0, r7, c1, c1, 0
  54         bic     r8, r7, #1
  55         mcr     p15, 0, r8, c1, c1, 0
  56         isb
  57
  58         @ Validate reason based on IAR and acknowledge
  59         movw    r8, #(GICC_BASE & 0xffff)
  60         movt    r8, #(GICC_BASE >> 16)
  61         ldr     r9, [r8, #GICC_IAR]
  62         movw    r10, #0x3ff
  63         movt    r10, #0
  64         cmp     r9, r10                 @ skip spurious interrupt 1023
  65         beq     out
  66         movw    r10, #0x3fe             @ ...and 1022
  67         cmp     r9, r10
  68         beq     out
  69         str     r9, [r8, #GICC_EOIR]    @ acknowledge the interrupt
  70         dsb
  71
  72         @ Compute CPU number
  73         lsr     r9, r9, #10
  74         and     r9, r9, #0xf
  75
  76         movw    r8, #(SUNXI_CPUCFG_BASE & 0xffff)
  77         movt    r8, #(SUNXI_CPUCFG_BASE >> 16)
  78
  79         @ Wait for the core to enter WFI
  80         lsl     r11, r9, #6             @ x64
  81         add     r11, r11, r8
  82
  83 1:      ldr     r10, [r11, #0x48]
  84         tst     r10, #(1 << 2)
  85         bne     2f
  86         timer_wait r10, ONE_MS
  87         b       1b
  88
  89         @ Reset CPU
  90 2:      mov     r10, #0
  91         str     r10, [r11, #0x40]
  92
  93         @ Lock CPU
  94         mov     r10, #1
  95         lsl     r11, r10, r9            @ r11 is now CPU mask
  96         ldr     r10, [r8, #0x1e4]
  97         bic     r10, r10, r11
  98         str     r10, [r8, #0x1e4]
  99
 100         movw    r8, #(SUNXI_PRCM_BASE & 0xffff)
 101         movt    r8, #(SUNXI_PRCM_BASE >> 16)
 102
 103         @ Set power gating
 104         ldr     r10, [r8, #0x100]
 105         orr     r10, r10, r11
 106         str     r10, [r8, #0x100]
 107         timer_wait r10, ONE_MS
 108
 109 #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
 110         @ Activate power clamp
 111         lsl     r12, r9, #2             @ x4
 112         add     r12, r12, r8
 113         mov     r10, #0xff
 114         str     r10, [r12, #0x140]
 115 #endif
 116
 117         movw    r8, #(SUNXI_CPUCFG_BASE & 0xffff)
 118         movt    r8, #(SUNXI_CPUCFG_BASE >> 16)
 119
 120         @ Unlock CPU
 121         ldr     r10, [r8, #0x1e4]
 122         orr     r10, r10, r11
 123         str     r10, [r8, #0x1e4]
 124
 125         @ Restore security level
 126 out:    mcr     p15, 0, r7, c1, c1, 0
 127
 128         pop     {r0-r12}
 129         subs    pc, lr, #4
 130
 131         @ r1 = target CPU
 132         @ r2 = target PC
 133 .globl  psci_cpu_on
 134 psci_cpu_on:
 135         push    {lr}
 136
 137         mov     r0, r1
 138         bl      psci_get_cpu_stack_top  @ get stack top of target CPU
 139         str     r2, [r0]                @ store target PC at stack top
 140         dsb
 141
 142         movw    r0, #(SUNXI_CPUCFG_BASE & 0xffff)
 143         movt    r0, #(SUNXI_CPUCFG_BASE >> 16)
 144
 145         @ CPU mask
 146         and     r1, r1, #3      @ only care about first cluster
 147         mov     r4, #1
 148         lsl     r4, r4, r1
 149
 150         ldr     r6, =psci_cpu_entry
 151         str     r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
 152
 153         @ Assert reset on target CPU
 154         mov     r6, #0
 155         lsl     r5, r1, #6      @ 64 bytes per CPU
 156         add     r5, r5, #0x40   @ Offset from base
 157         add     r5, r5, r0      @ CPU control block
 158         str     r6, [r5]        @ Reset CPU
 159
 160         @ l1 invalidate
 161         ldr     r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
 162         bic     r6, r6, r4
 163         str     r6, [r0, #0x184]
 164
 165         @ Lock CPU (Disable external debug access)
 166         ldr     r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
 167         bic     r6, r6, r4
 168         str     r6, [r0, #0x1e4]
 169
 170         movw    r0, #(SUNXI_PRCM_BASE & 0xffff)
 171         movt    r0, #(SUNXI_PRCM_BASE >> 16)
 172
 173 #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
 174         @ Release power clamp
 175         lsl     r5, r1, #2      @ 1 register per CPU
 176         add     r5, r5, r0      @ PRCM
 177         movw    r6, #0x1ff
 178         movt    r6, #0
 179 1:      lsrs    r6, r6, #1
 180         str     r6, [r5, #0x140] @ CPUx_PWR_CLAMP
 181         bne     1b
 182 #endif
 183
 184         timer_wait r6, TEN_MS
 185
 186         @ Clear power gating
 187         ldr     r6, [r0, #0x100] @ CPU_PWROFF_GATING
 188         bic     r6, r6, r4
 189         str     r6, [r0, #0x100]
 190
 191         @ re-calculate CPU control register address
 192         movw    r0, #(SUNXI_CPUCFG_BASE & 0xffff)
 193         movt    r0, #(SUNXI_CPUCFG_BASE >> 16)
 194
 195         @ Deassert reset on target CPU
 196         mov     r6, #3
 197         lsl     r5, r1, #6      @ 64 bytes per CPU
 198         add     r5, r5, #0x40   @ Offset from base
 199         add     r5, r5, r0      @ CPU control block
 200         str     r6, [r5]
 201
 202         @ Unlock CPU (Enable external debug access)
 203         ldr     r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
 204         orr     r6, r6, r4
 205         str     r6, [r0, #0x1e4]
 206
 207         mov     r0, #ARM_PSCI_RET_SUCCESS       @ Return PSCI_RET_SUCCESS
 208         pop     {pc}
 209
 210 .globl  psci_cpu_off
 211 psci_cpu_off:
 212         bl      psci_cpu_off_common
 213
 214         @ Ask CPU0 to pull the rug...
 215         movw    r0, #(GICD_BASE & 0xffff)
 216         movt    r0, #(GICD_BASE >> 16)
 217         movw    r1, #15                         @ SGI15
 218         movt    r1, #1                          @ Target is CPU0
 219         str     r1, [r0, #GICD_SGIR]
 220         dsb
 221
 222 1:      wfi
 223         b       1b
 224
 225 .globl  psci_arch_init
 226 psci_arch_init:
 227         mov     r6, lr
 228
 229         movw    r4, #(GICD_BASE & 0xffff)
 230         movt    r4, #(GICD_BASE >> 16)
 231
 232         ldr     r5, [r4, #GICD_IGROUPRn]
 233         bic     r5, r5, #(1 << 15)      @ SGI15 as Group-0
 234         str     r5, [r4, #GICD_IGROUPRn]
 235
 236         mov     r5, #0                  @ Set SGI15 priority to 0
 237         strb    r5, [r4, #(GICD_IPRIORITYRn + 15)]
 238
 239         add     r4, r4, #0x1000         @ GICC address
 240
 241         mov     r5, #0xff
 242         str     r5, [r4, #GICC_PMR]     @ Be cool with non-secure
 243
 244         ldr     r5, [r4, #GICC_CTLR]
 245         orr     r5, r5, #(1 << 3)       @ Switch FIQEn on
 246         str     r5, [r4, #GICC_CTLR]
 247
 248         mrc     p15, 0, r5, c1, c1, 0   @ Read SCR
 249         orr     r5, r5, #4              @ Enable FIQ in monitor mode
 250         bic     r5, r5, #1              @ Secure mode
 251         mcr     p15, 0, r5, c1, c1, 0   @ Write SCR
 252         isb
 253
 254         bl      psci_get_cpu_id         @ CPU ID => r0
 255         bl      psci_get_cpu_stack_top  @ stack top => r0
 256         mov     sp, r0
 257
 258         bx      r6
 259
 260         .globl psci_text_end
 261 psci_text_end:
 262         .popsection