arch/arm/cpu/armv7/tegra2/warmboot_avp.h

   1 /*
   2  * (C) Copyright 2010, 2011
   3  * NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef _WARMBOOT_AVP_H_
  25 #define _WARMBOOT_AVP_H_
  26
  27 #define TEGRA_DEV_L                     0
  28 #define TEGRA_DEV_H                     1
  29 #define TEGRA_DEV_U                     2
  30
  31 #define SIMPLE_PLLX                     (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
  32 #define SIMPLE_PLLE                     (CLOCK_ID_EPCI - CLOCK_ID_FIRST_SIMPLE)
  33
  34 #define TIMER_USEC_CNTR                 (NV_PA_TMRUS_BASE + 0)
  35 #define TIMER_USEC_CFG                  (NV_PA_TMRUS_BASE + 4)
  36
  37 #define USEC_CFG_DIVISOR_MASK           0xffff
  38
  39 #define CONFIG_CTL_TBE                  (1 << 7)
  40 #define CONFIG_CTL_JTAG                 (1 << 6)
  41
  42 #define CPU_RST                         (1 << 0)
  43 #define CLK_ENB_CPU                     (1 << 0)
  44 #define SWR_TRIG_SYS_RST                (1 << 2)
  45 #define SWR_CSITE_RST                   (1 << 9)
  46
  47 #define PWRGATE_STATUS_CPU              (1 << 0)
  48 #define PWRGATE_TOGGLE_PARTID_CPU       (0 << 0)
  49 #define PWRGATE_TOGGLE_START            (1 << 8)
  50
  51 #define CPU_CMPLX_CPU_BRIDGE_CLKDIV_4   (3 << 0)
  52 #define CPU_CMPLX_CPU0_CLK_STP_STOP     (1 << 8)
  53 #define CPU_CMPLX_CPU0_CLK_STP_RUN      (0 << 8)
  54 #define CPU_CMPLX_CPU1_CLK_STP_STOP     (1 << 9)
  55 #define CPU_CMPLX_CPU1_CLK_STP_RUN      (0 << 9)
  56
  57 #define CPU_CMPLX_CPURESET0             (1 << 0)
  58 #define CPU_CMPLX_CPURESET1             (1 << 1)
  59 #define CPU_CMPLX_DERESET0              (1 << 4)
  60 #define CPU_CMPLX_DERESET1              (1 << 5)
  61 #define CPU_CMPLX_DBGRESET0             (1 << 12)
  62 #define CPU_CMPLX_DBGRESET1             (1 << 13)
  63
  64 #define PLLM_OUT1_RSTN_RESET_DISABLE    (1 << 0)
  65 #define PLLM_OUT1_CLKEN_ENABLE          (1 << 1)
  66 #define PLLM_OUT1_RATIO_VAL_8           (8 << 8)
  67
  68 #define SCLK_SYS_STATE_IDLE             (1 << 28)
  69 #define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1    (7 << 12)
  70 #define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1    (7 << 8)
  71 #define SCLK_SWAKE_RUN_SRC_PLLM_OUT1    (7 << 4)
  72 #define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1   (7 << 0)
  73
  74 #define EVENT_ZERO_VAL_20               (20 << 0)
  75 #define EVENT_MSEC                      (1 << 24)
  76 #define EVENT_JTAG                      (1 << 28)
  77 #define EVENT_MODE_STOP                 (2 << 29)
  78
  79 #define CCLK_PLLP_BURST_POLICY          0x20004444
  80
  81 #endif