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[people/ms/u-boot.git] / arch / arm / cpu / armv7 / tegra20 / clock.c
1 /*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * See file CREDITS for list of people who contributed to this
4 * project.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22 /* Tegra20 Clock control functions */
23
24 #include <asm/io.h>
25 #include <asm/arch/clk_rst.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/timer.h>
28 #include <asm/arch/tegra20.h>
29 #include <common.h>
30 #include <div64.h>
31 #include <fdtdec.h>
32
33 /*
34 * This is our record of the current clock rate of each clock. We don't
35 * fill all of these in since we are only really interested in clocks which
36 * we use as parents.
37 */
38 static unsigned pll_rate[CLOCK_ID_COUNT];
39
40 /*
41 * The oscillator frequency is fixed to one of four set values. Based on this
42 * the other clocks are set up appropriately.
43 */
44 static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
45 13000000,
46 19200000,
47 12000000,
48 26000000,
49 };
50
51 /*
52 * Clock types that we can use as a source. The Tegra20 has muxes for the
53 * peripheral clocks, and in most cases there are four options for the clock
54 * source. This gives us a clock 'type' and exploits what commonality exists
55 * in the device.
56 *
57 * Letters are obvious, except for T which means CLK_M, and S which means the
58 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
59 * datasheet) and PLL_M are different things. The former is the basic
60 * clock supplied to the SOC from an external oscillator. The latter is the
61 * memory clock PLL.
62 *
63 * See definitions in clock_id in the header file.
64 */
65 enum clock_type_id {
66 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
67 CLOCK_TYPE_MCPA, /* and so on */
68 CLOCK_TYPE_MCPT,
69 CLOCK_TYPE_PCM,
70 CLOCK_TYPE_PCMT,
71 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
72 CLOCK_TYPE_PCXTS,
73 CLOCK_TYPE_PDCT,
74
75 CLOCK_TYPE_COUNT,
76 CLOCK_TYPE_NONE = -1, /* invalid clock type */
77 };
78
79 /* return 1 if a peripheral ID is in range */
80 #define clock_type_id_isvalid(id) ((id) >= 0 && \
81 (id) < CLOCK_TYPE_COUNT)
82
83 char pllp_valid = 1; /* PLLP is set up correctly */
84
85 enum {
86 CLOCK_MAX_MUX = 4 /* number of source options for each clock */
87 };
88
89 /*
90 * Clock source mux for each clock type. This just converts our enum into
91 * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
92 * is special as it has 5 sources. Since it also has a different number of
93 * bits in its register for the source, we just handle it with a special
94 * case in the code.
95 */
96 #define CLK(x) CLOCK_ID_ ## x
97 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
98 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
99 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
100 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
101 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
102 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
103 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
104 { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
105 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
106 };
107
108 /*
109 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
110 * not in the header file since it is for purely internal use - we want
111 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
112 * confusion bewteen PERIPH_ID_... and PERIPHC_...
113 *
114 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
115 * confusing.
116 *
117 * Note to SOC vendors: perhaps define a unified numbering for peripherals and
118 * use it for reset, clock enable, clock source/divider and even pinmuxing
119 * if you can.
120 */
121 enum periphc_internal_id {
122 /* 0x00 */
123 PERIPHC_I2S1,
124 PERIPHC_I2S2,
125 PERIPHC_SPDIF_OUT,
126 PERIPHC_SPDIF_IN,
127 PERIPHC_PWM,
128 PERIPHC_SPI1,
129 PERIPHC_SPI2,
130 PERIPHC_SPI3,
131
132 /* 0x08 */
133 PERIPHC_XIO,
134 PERIPHC_I2C1,
135 PERIPHC_DVC_I2C,
136 PERIPHC_TWC,
137 PERIPHC_0c,
138 PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
139 PERIPHC_DISP1,
140 PERIPHC_DISP2,
141
142 /* 0x10 */
143 PERIPHC_CVE,
144 PERIPHC_IDE0,
145 PERIPHC_VI,
146 PERIPHC_1c,
147 PERIPHC_SDMMC1,
148 PERIPHC_SDMMC2,
149 PERIPHC_G3D,
150 PERIPHC_G2D,
151
152 /* 0x18 */
153 PERIPHC_NDFLASH,
154 PERIPHC_SDMMC4,
155 PERIPHC_VFIR,
156 PERIPHC_EPP,
157 PERIPHC_MPE,
158 PERIPHC_MIPI,
159 PERIPHC_UART1,
160 PERIPHC_UART2,
161
162 /* 0x20 */
163 PERIPHC_HOST1X,
164 PERIPHC_21,
165 PERIPHC_TVO,
166 PERIPHC_HDMI,
167 PERIPHC_24,
168 PERIPHC_TVDAC,
169 PERIPHC_I2C2,
170 PERIPHC_EMC,
171
172 /* 0x28 */
173 PERIPHC_UART3,
174 PERIPHC_29,
175 PERIPHC_VI_SENSOR,
176 PERIPHC_2b,
177 PERIPHC_2c,
178 PERIPHC_SPI4,
179 PERIPHC_I2C3,
180 PERIPHC_SDMMC3,
181
182 /* 0x30 */
183 PERIPHC_UART4,
184 PERIPHC_UART5,
185 PERIPHC_VDE,
186 PERIPHC_OWR,
187 PERIPHC_NOR,
188 PERIPHC_CSITE,
189
190 PERIPHC_COUNT,
191
192 PERIPHC_NONE = -1,
193 };
194
195 /* return 1 if a periphc_internal_id is in range */
196 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
197 (id) < PERIPHC_COUNT)
198
199 /*
200 * Clock type for each peripheral clock source. We put the name in each
201 * record just so it is easy to match things up
202 */
203 #define TYPE(name, type) type
204 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
205 /* 0x00 */
206 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
207 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
208 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
209 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
210 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
211 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
212 TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
213 TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
214
215 /* 0x08 */
216 TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
217 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
218 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
219 TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
220 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
221 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
222 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
223 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
224
225 /* 0x10 */
226 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
227 TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
228 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
229 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
230 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
231 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
232 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
233 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
234
235 /* 0x18 */
236 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
237 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
238 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
239 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
240 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
241 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
242 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
243 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
244
245 /* 0x20 */
246 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
247 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
248 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
249 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
250 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
251 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
252 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
253 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
254
255 /* 0x28 */
256 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
257 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
258 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
259 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
260 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
261 TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
262 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
263 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
264
265 /* 0x30 */
266 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
267 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
268 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
269 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
270 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
271 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
272 };
273
274 /*
275 * This array translates a periph_id to a periphc_internal_id
276 *
277 * Not present/matched up:
278 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
279 * SPDIF - which is both 0x08 and 0x0c
280 *
281 */
282 #define NONE(name) (-1)
283 #define OFFSET(name, value) PERIPHC_ ## name
284 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
285 /* Low word: 31:0 */
286 NONE(CPU),
287 NONE(RESERVED1),
288 NONE(RESERVED2),
289 NONE(AC97),
290 NONE(RTC),
291 NONE(TMR),
292 PERIPHC_UART1,
293 PERIPHC_UART2, /* and vfir 0x68 */
294
295 /* 0x08 */
296 NONE(GPIO),
297 PERIPHC_SDMMC2,
298 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
299 PERIPHC_I2S1,
300 PERIPHC_I2C1,
301 PERIPHC_NDFLASH,
302 PERIPHC_SDMMC1,
303 PERIPHC_SDMMC4,
304
305 /* 0x10 */
306 PERIPHC_TWC,
307 PERIPHC_PWM,
308 PERIPHC_I2S2,
309 PERIPHC_EPP,
310 PERIPHC_VI,
311 PERIPHC_G2D,
312 NONE(USBD),
313 NONE(ISP),
314
315 /* 0x18 */
316 PERIPHC_G3D,
317 PERIPHC_IDE0,
318 PERIPHC_DISP2,
319 PERIPHC_DISP1,
320 PERIPHC_HOST1X,
321 NONE(VCP),
322 NONE(RESERVED30),
323 NONE(CACHE2),
324
325 /* Middle word: 63:32 */
326 NONE(MEM),
327 NONE(AHBDMA),
328 NONE(APBDMA),
329 NONE(RESERVED35),
330 NONE(KBC),
331 NONE(STAT_MON),
332 NONE(PMC),
333 NONE(FUSE),
334
335 /* 0x28 */
336 NONE(KFUSE),
337 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
338 PERIPHC_NOR,
339 PERIPHC_SPI1,
340 PERIPHC_SPI2,
341 PERIPHC_XIO,
342 PERIPHC_SPI3,
343 PERIPHC_DVC_I2C,
344
345 /* 0x30 */
346 NONE(DSI),
347 PERIPHC_TVO, /* also CVE 0x40 */
348 PERIPHC_MIPI,
349 PERIPHC_HDMI,
350 PERIPHC_CSITE,
351 PERIPHC_TVDAC,
352 PERIPHC_I2C2,
353 PERIPHC_UART3,
354
355 /* 0x38 */
356 NONE(RESERVED56),
357 PERIPHC_EMC,
358 NONE(USB2),
359 NONE(USB3),
360 PERIPHC_MPE,
361 PERIPHC_VDE,
362 NONE(BSEA),
363 NONE(BSEV),
364
365 /* Upper word 95:64 */
366 NONE(SPEEDO),
367 PERIPHC_UART4,
368 PERIPHC_UART5,
369 PERIPHC_I2C3,
370 PERIPHC_SPI4,
371 PERIPHC_SDMMC3,
372 NONE(PCIE),
373 PERIPHC_OWR,
374
375 /* 0x48 */
376 NONE(AFI),
377 NONE(CORESIGHT),
378 NONE(RESERVED74),
379 NONE(AVPUCQ),
380 NONE(RESERVED76),
381 NONE(RESERVED77),
382 NONE(RESERVED78),
383 NONE(RESERVED79),
384
385 /* 0x50 */
386 NONE(RESERVED80),
387 NONE(RESERVED81),
388 NONE(RESERVED82),
389 NONE(RESERVED83),
390 NONE(IRAMA),
391 NONE(IRAMB),
392 NONE(IRAMC),
393 NONE(IRAMD),
394
395 /* 0x58 */
396 NONE(CRAM2),
397 };
398
399 /*
400 * Get the oscillator frequency, from the corresponding hardware configuration
401 * field.
402 */
403 enum clock_osc_freq clock_get_osc_freq(void)
404 {
405 struct clk_rst_ctlr *clkrst =
406 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
407 u32 reg;
408
409 reg = readl(&clkrst->crc_osc_ctrl);
410 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
411 }
412
413 int clock_get_osc_bypass(void)
414 {
415 struct clk_rst_ctlr *clkrst =
416 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
417 u32 reg;
418
419 reg = readl(&clkrst->crc_osc_ctrl);
420 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
421 }
422
423 /* Returns a pointer to the registers of the given pll */
424 static struct clk_pll *get_pll(enum clock_id clkid)
425 {
426 struct clk_rst_ctlr *clkrst =
427 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
428
429 assert(clock_id_is_pll(clkid));
430 return &clkrst->crc_pll[clkid];
431 }
432
433 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
434 u32 *divp, u32 *cpcon, u32 *lfcon)
435 {
436 struct clk_pll *pll = get_pll(clkid);
437 u32 data;
438
439 assert(clkid != CLOCK_ID_USB);
440
441 /* Safety check, adds to code size but is small */
442 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
443 return -1;
444 data = readl(&pll->pll_base);
445 *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
446 *divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
447 *divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
448 data = readl(&pll->pll_misc);
449 *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
450 *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
451
452 return 0;
453 }
454
455 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
456 u32 divp, u32 cpcon, u32 lfcon)
457 {
458 struct clk_pll *pll = get_pll(clkid);
459 u32 data;
460
461 /*
462 * We cheat by treating all PLL (except PLLU) in the same fashion.
463 * This works only because:
464 * - same fields are always mapped at same offsets, except DCCON
465 * - DCCON is always 0, doesn't conflict
466 * - M,N, P of PLLP values are ignored for PLLP
467 */
468 data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
469 writel(data, &pll->pll_misc);
470
471 data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
472 (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
473
474 if (clkid == CLOCK_ID_USB)
475 data |= divp << PLLU_VCO_FREQ_SHIFT;
476 else
477 data |= divp << PLL_DIVP_SHIFT;
478 writel(data, &pll->pll_base);
479
480 /* calculate the stable time */
481 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
482 }
483
484 /* return 1 if a peripheral ID is in range and valid */
485 static int clock_periph_id_isvalid(enum periph_id id)
486 {
487 if (id < PERIPH_ID_FIRST || id >= PERIPH_ID_COUNT)
488 printf("Peripheral id %d out of range\n", id);
489 else {
490 switch (id) {
491 case PERIPH_ID_RESERVED1:
492 case PERIPH_ID_RESERVED2:
493 case PERIPH_ID_RESERVED30:
494 case PERIPH_ID_RESERVED35:
495 case PERIPH_ID_RESERVED56:
496 case PERIPH_ID_RESERVED74:
497 case PERIPH_ID_RESERVED76:
498 case PERIPH_ID_RESERVED77:
499 case PERIPH_ID_RESERVED78:
500 case PERIPH_ID_RESERVED79:
501 case PERIPH_ID_RESERVED80:
502 case PERIPH_ID_RESERVED81:
503 case PERIPH_ID_RESERVED82:
504 case PERIPH_ID_RESERVED83:
505 printf("Peripheral id %d is reserved\n", id);
506 break;
507 default:
508 return 1;
509 }
510 }
511 return 0;
512 }
513
514 /* Returns a pointer to the clock source register for a peripheral */
515 static u32 *get_periph_source_reg(enum periph_id periph_id)
516 {
517 struct clk_rst_ctlr *clkrst =
518 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
519 enum periphc_internal_id internal_id;
520
521 assert(clock_periph_id_isvalid(periph_id));
522 internal_id = periph_id_to_internal_id[periph_id];
523 assert(internal_id != -1);
524 return &clkrst->crc_clk_src[internal_id];
525 }
526
527 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
528 unsigned divisor)
529 {
530 u32 *reg = get_periph_source_reg(periph_id);
531 u32 value;
532
533 value = readl(reg);
534
535 value &= ~OUT_CLK_SOURCE_MASK;
536 value |= source << OUT_CLK_SOURCE_SHIFT;
537
538 value &= ~OUT_CLK_DIVISOR_MASK;
539 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
540
541 writel(value, reg);
542 }
543
544 void clock_ll_set_source(enum periph_id periph_id, unsigned source)
545 {
546 u32 *reg = get_periph_source_reg(periph_id);
547
548 clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
549 source << OUT_CLK_SOURCE_SHIFT);
550 }
551
552 /**
553 * Given the parent's rate and the required rate for the children, this works
554 * out the peripheral clock divider to use, in 7.1 binary format.
555 *
556 * @param divider_bits number of divider bits (8 or 16)
557 * @param parent_rate clock rate of parent clock in Hz
558 * @param rate required clock rate for this clock
559 * @return divider which should be used
560 */
561 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
562 unsigned long rate)
563 {
564 u64 divider = parent_rate * 2;
565 unsigned max_divider = 1 << divider_bits;
566
567 divider += rate - 1;
568 do_div(divider, rate);
569
570 if ((s64)divider - 2 < 0)
571 return 0;
572
573 if ((s64)divider - 2 >= max_divider)
574 return -1;
575
576 return divider - 2;
577 }
578
579 /**
580 * Given the parent's rate and the divider in 7.1 format, this works out the
581 * resulting peripheral clock rate.
582 *
583 * @param parent_rate clock rate of parent clock in Hz
584 * @param divider which should be used in 7.1 format
585 * @return effective clock rate of peripheral
586 */
587 static unsigned long get_rate_from_divider(unsigned long parent_rate,
588 int divider)
589 {
590 u64 rate;
591
592 rate = (u64)parent_rate * 2;
593 do_div(rate, divider + 2);
594 return rate;
595 }
596
597 unsigned long clock_get_periph_rate(enum periph_id periph_id,
598 enum clock_id parent)
599 {
600 u32 *reg = get_periph_source_reg(periph_id);
601
602 return get_rate_from_divider(pll_rate[parent],
603 (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
604 }
605
606 /**
607 * Find the best available 7.1 format divisor given a parent clock rate and
608 * required child clock rate. This function assumes that a second-stage
609 * divisor is available which can divide by powers of 2 from 1 to 256.
610 *
611 * @param divider_bits number of divider bits (8 or 16)
612 * @param parent_rate clock rate of parent clock in Hz
613 * @param rate required clock rate for this clock
614 * @param extra_div value for the second-stage divisor (not set if this
615 * function returns -1.
616 * @return divider which should be used, or -1 if nothing is valid
617 *
618 */
619 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
620 unsigned long rate, int *extra_div)
621 {
622 int shift;
623 int best_divider = -1;
624 int best_error = rate;
625
626 /* try dividers from 1 to 256 and find closest match */
627 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
628 unsigned divided_parent = parent_rate >> shift;
629 int divider = clk_get_divider(divider_bits, divided_parent,
630 rate);
631 unsigned effective_rate = get_rate_from_divider(divided_parent,
632 divider);
633 int error = rate - effective_rate;
634
635 /* Given a valid divider, look for the lowest error */
636 if (divider != -1 && error < best_error) {
637 best_error = error;
638 *extra_div = 1 << shift;
639 best_divider = divider;
640 }
641 }
642
643 /* return what we found - *extra_div will already be set */
644 return best_divider;
645 }
646
647 /**
648 * Given a peripheral ID and the required source clock, this returns which
649 * value should be programmed into the source mux for that peripheral.
650 *
651 * There is special code here to handle the one source type with 5 sources.
652 *
653 * @param periph_id peripheral to start
654 * @param source PLL id of required parent clock
655 * @param mux_bits Set to number of bits in mux register: 2 or 4
656 * @param divider_bits Set to number of divider bits (8 or 16)
657 * @return mux value (0-4, or -1 if not found)
658 */
659 static int get_periph_clock_source(enum periph_id periph_id,
660 enum clock_id parent, int *mux_bits, int *divider_bits)
661 {
662 enum clock_type_id type;
663 enum periphc_internal_id internal_id;
664 int mux;
665
666 assert(clock_periph_id_isvalid(periph_id));
667
668 internal_id = periph_id_to_internal_id[periph_id];
669 assert(periphc_internal_id_isvalid(internal_id));
670
671 type = clock_periph_type[internal_id];
672 assert(clock_type_id_isvalid(type));
673
674 /*
675 * Special cases here for the clock with a 4-bit source mux and I2C
676 * with its 16-bit divisor
677 */
678 if (type == CLOCK_TYPE_PCXTS)
679 *mux_bits = 4;
680 else
681 *mux_bits = 2;
682 if (type == CLOCK_TYPE_PCMT16)
683 *divider_bits = 16;
684 else
685 *divider_bits = 8;
686
687 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
688 if (clock_source[type][mux] == parent)
689 return mux;
690
691 /*
692 * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
693 * which is not in our table. If not, then they are asking for a
694 * source which this peripheral can't access through its mux.
695 */
696 assert(type == CLOCK_TYPE_PCXTS);
697 assert(parent == CLOCK_ID_SFROM32KHZ);
698 if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
699 return 4; /* mux value for this clock */
700
701 /* if we get here, either us or the caller has made a mistake */
702 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
703 parent);
704 return -1;
705 }
706
707 /**
708 * Adjust peripheral PLL to use the given divider and source.
709 *
710 * @param periph_id peripheral to adjust
711 * @param source Source number (0-3 or 0-7)
712 * @param mux_bits Number of mux bits (2 or 4)
713 * @param divider Required divider in 7.1 or 15.1 format
714 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
715 * for this peripheral)
716 */
717 static int adjust_periph_pll(enum periph_id periph_id, int source,
718 int mux_bits, unsigned divider)
719 {
720 u32 *reg = get_periph_source_reg(periph_id);
721
722 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
723 divider << OUT_CLK_DIVISOR_SHIFT);
724 udelay(1);
725
726 /* work out the source clock and set it */
727 if (source < 0)
728 return -1;
729 if (mux_bits == 4) {
730 clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
731 source << OUT_CLK_SOURCE4_SHIFT);
732 } else {
733 clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
734 source << OUT_CLK_SOURCE_SHIFT);
735 }
736 udelay(2);
737 return 0;
738 }
739
740 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
741 enum clock_id parent, unsigned rate, int *extra_div)
742 {
743 unsigned effective_rate;
744 int mux_bits, divider_bits, source;
745 int divider;
746
747 /* work out the source clock and set it */
748 source = get_periph_clock_source(periph_id, parent, &mux_bits,
749 &divider_bits);
750
751 if (extra_div)
752 divider = find_best_divider(divider_bits, pll_rate[parent],
753 rate, extra_div);
754 else
755 divider = clk_get_divider(divider_bits, pll_rate[parent],
756 rate);
757 assert(divider >= 0);
758 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
759 return -1U;
760 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
761 get_periph_source_reg(periph_id),
762 readl(get_periph_source_reg(periph_id)));
763
764 /* Check what we ended up with. This shouldn't matter though */
765 effective_rate = clock_get_periph_rate(periph_id, parent);
766 if (extra_div)
767 effective_rate /= *extra_div;
768 if (rate != effective_rate)
769 debug("Requested clock rate %u not honored (got %u)\n",
770 rate, effective_rate);
771 return effective_rate;
772 }
773
774 unsigned clock_start_periph_pll(enum periph_id periph_id,
775 enum clock_id parent, unsigned rate)
776 {
777 unsigned effective_rate;
778
779 reset_set_enable(periph_id, 1);
780 clock_enable(periph_id);
781
782 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
783 NULL);
784
785 reset_set_enable(periph_id, 0);
786 return effective_rate;
787 }
788
789 void clock_set_enable(enum periph_id periph_id, int enable)
790 {
791 struct clk_rst_ctlr *clkrst =
792 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
793 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
794 u32 reg;
795
796 /* Enable/disable the clock to this peripheral */
797 assert(clock_periph_id_isvalid(periph_id));
798 reg = readl(clk);
799 if (enable)
800 reg |= PERIPH_MASK(periph_id);
801 else
802 reg &= ~PERIPH_MASK(periph_id);
803 writel(reg, clk);
804 }
805
806 void clock_enable(enum periph_id clkid)
807 {
808 clock_set_enable(clkid, 1);
809 }
810
811 void clock_disable(enum periph_id clkid)
812 {
813 clock_set_enable(clkid, 0);
814 }
815
816 void reset_set_enable(enum periph_id periph_id, int enable)
817 {
818 struct clk_rst_ctlr *clkrst =
819 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
820 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
821 u32 reg;
822
823 /* Enable/disable reset to the peripheral */
824 assert(clock_periph_id_isvalid(periph_id));
825 reg = readl(reset);
826 if (enable)
827 reg |= PERIPH_MASK(periph_id);
828 else
829 reg &= ~PERIPH_MASK(periph_id);
830 writel(reg, reset);
831 }
832
833 void reset_periph(enum periph_id periph_id, int us_delay)
834 {
835 /* Put peripheral into reset */
836 reset_set_enable(periph_id, 1);
837 udelay(us_delay);
838
839 /* Remove reset */
840 reset_set_enable(periph_id, 0);
841
842 udelay(us_delay);
843 }
844
845 void reset_cmplx_set_enable(int cpu, int which, int reset)
846 {
847 struct clk_rst_ctlr *clkrst =
848 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
849 u32 mask;
850
851 /* Form the mask, which depends on the cpu chosen. Tegra20 has 2 */
852 assert(cpu >= 0 && cpu < 2);
853 mask = which << cpu;
854
855 /* either enable or disable those reset for that CPU */
856 if (reset)
857 writel(mask, &clkrst->crc_cpu_cmplx_set);
858 else
859 writel(mask, &clkrst->crc_cpu_cmplx_clr);
860 }
861
862 unsigned clock_get_rate(enum clock_id clkid)
863 {
864 struct clk_pll *pll;
865 u32 base;
866 u32 divm;
867 u64 parent_rate;
868 u64 rate;
869
870 parent_rate = osc_freq[clock_get_osc_freq()];
871 if (clkid == CLOCK_ID_OSC)
872 return parent_rate;
873
874 pll = get_pll(clkid);
875 base = readl(&pll->pll_base);
876
877 /* Oh for bf_unpack()... */
878 rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
879 divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
880 if (clkid == CLOCK_ID_USB)
881 divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
882 else
883 divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
884 do_div(rate, divm);
885 return rate;
886 }
887
888 /**
889 * Set the output frequency you want for each PLL clock.
890 * PLL output frequencies are programmed by setting their N, M and P values.
891 * The governing equations are:
892 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
893 * where Fo is the output frequency from the PLL.
894 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
895 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
896 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
897 *
898 * @param n PLL feedback divider(DIVN)
899 * @param m PLL input divider(DIVN)
900 * @param p post divider(DIVP)
901 * @param cpcon base PLL charge pump(CPCON)
902 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
903 * be overriden), 1 if PLL is already correct
904 */
905 static int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
906 {
907 u32 base_reg;
908 u32 misc_reg;
909 struct clk_pll *pll;
910
911 pll = get_pll(clkid);
912
913 base_reg = readl(&pll->pll_base);
914
915 /* Set BYPASS, m, n and p to PLL_BASE */
916 base_reg &= ~PLL_DIVM_MASK;
917 base_reg |= m << PLL_DIVM_SHIFT;
918
919 base_reg &= ~PLL_DIVN_MASK;
920 base_reg |= n << PLL_DIVN_SHIFT;
921
922 base_reg &= ~PLL_DIVP_MASK;
923 base_reg |= p << PLL_DIVP_SHIFT;
924
925 if (clkid == CLOCK_ID_PERIPH) {
926 /*
927 * If the PLL is already set up, check that it is correct
928 * and record this info for clock_verify() to check.
929 */
930 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
931 base_reg |= PLL_ENABLE_MASK;
932 if (base_reg != readl(&pll->pll_base))
933 pllp_valid = 0;
934 return pllp_valid ? 1 : -1;
935 }
936 base_reg |= PLL_BASE_OVRRIDE_MASK;
937 }
938
939 base_reg |= PLL_BYPASS_MASK;
940 writel(base_reg, &pll->pll_base);
941
942 /* Set cpcon to PLL_MISC */
943 misc_reg = readl(&pll->pll_misc);
944 misc_reg &= ~PLL_CPCON_MASK;
945 misc_reg |= cpcon << PLL_CPCON_SHIFT;
946 writel(misc_reg, &pll->pll_misc);
947
948 /* Enable PLL */
949 base_reg |= PLL_ENABLE_MASK;
950 writel(base_reg, &pll->pll_base);
951
952 /* Disable BYPASS */
953 base_reg &= ~PLL_BYPASS_MASK;
954 writel(base_reg, &pll->pll_base);
955
956 return 0;
957 }
958
959 void clock_ll_start_uart(enum periph_id periph_id)
960 {
961 /* Assert UART reset and enable clock */
962 reset_set_enable(periph_id, 1);
963 clock_enable(periph_id);
964 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
965
966 /* wait for 2us */
967 udelay(2);
968
969 /* De-assert reset to UART */
970 reset_set_enable(periph_id, 0);
971 }
972
973 #ifdef CONFIG_OF_CONTROL
974 /*
975 * Convert a device tree clock ID to our peripheral ID. They are mostly
976 * the same but we are very cautious so we check that a valid clock ID is
977 * provided.
978 *
979 * @param clk_id Clock ID according to tegra20 device tree binding
980 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
981 */
982 static enum periph_id clk_id_to_periph_id(int clk_id)
983 {
984 if (clk_id > 95)
985 return PERIPH_ID_NONE;
986
987 switch (clk_id) {
988 case 1:
989 case 2:
990 case 7:
991 case 10:
992 case 20:
993 case 30:
994 case 35:
995 case 49:
996 case 56:
997 case 74:
998 case 76:
999 case 77:
1000 case 78:
1001 case 79:
1002 case 80:
1003 case 81:
1004 case 82:
1005 case 83:
1006 case 91:
1007 case 95:
1008 return PERIPH_ID_NONE;
1009 default:
1010 return clk_id;
1011 }
1012 }
1013
1014 int clock_decode_periph_id(const void *blob, int node)
1015 {
1016 enum periph_id id;
1017 u32 cell[2];
1018 int err;
1019
1020 err = fdtdec_get_int_array(blob, node, "clocks", cell,
1021 ARRAY_SIZE(cell));
1022 if (err)
1023 return -1;
1024 id = clk_id_to_periph_id(cell[1]);
1025 assert(clock_periph_id_isvalid(id));
1026 return id;
1027 }
1028 #endif /* CONFIG_OF_CONTROL */
1029
1030 int clock_verify(void)
1031 {
1032 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
1033 u32 reg = readl(&pll->pll_base);
1034
1035 if (!pllp_valid) {
1036 printf("Warning: PLLP %x is not correct\n", reg);
1037 return -1;
1038 }
1039 debug("PLLX %x is correct\n", reg);
1040 return 0;
1041 }
1042
1043 void clock_early_init(void)
1044 {
1045 /*
1046 * PLLP output frequency set to 216MHz
1047 * PLLC output frequency set to 600Mhz
1048 *
1049 * TODO: Can we calculate these values instead of hard-coding?
1050 */
1051 switch (clock_get_osc_freq()) {
1052 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
1053 clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
1054 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
1055 break;
1056
1057 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
1058 clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
1059 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
1060 break;
1061
1062 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
1063 clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
1064 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
1065 break;
1066 case CLOCK_OSC_FREQ_19_2:
1067 default:
1068 /*
1069 * These are not supported. It is too early to print a
1070 * message and the UART likely won't work anyway due to the
1071 * oscillator being wrong.
1072 */
1073 break;
1074 }
1075 }
1076
1077 void clock_init(void)
1078 {
1079 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
1080 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
1081 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
1082 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
1083 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
1084 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
1085 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
1086 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
1087 }
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