arch/arm/cpu/armv7/u8500/cpu.c

   1 /*
   2  * Copyright (C) 2012 Linaro Limited
   3  * Mathieu Poirier <mathieu.poirier@linaro.org>
   4  *
   5  * Based on original code from Joakim Axelsson at ST-Ericsson
   6  * (C) Copyright 2010 ST-Ericsson
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/prcmu.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/hardware.h>
  16
  17 #include <asm/arch/hardware.h>
  18
  19 #define CPUID_DB8500V1          0x411fc091
  20 #define CPUID_DB8500V2          0x412fc091
  21 #define ASICID_DB8500V11        0x008500A1
  22
  23 #define CACHE_CONTR_BASE        0xA0412000
  24 /* Cache controller register offsets
  25  * as found in ARM's technical reference manual
  26  */
  27 #define CACHE_INVAL_BY_WAY      (CACHE_CONTR_BASE + 0x77C)
  28 #define CACHE_LOCKDOWN_BY_D     (CACHE_CONTR_BASE + 0X900)
  29 #define CACHE_LOCKDOWN_BY_I     (CACHE_CONTR_BASE + 0X904)
  30
  31 static unsigned int read_asicid(void);
  32
  33 static inline unsigned int read_cpuid(void)
  34 {
  35         unsigned int val;
  36
  37         /* Main ID register (MIDR) */
  38         asm("mrc        p15, 0, %0, c0, c0, 0"
  39            : "=r" (val)
  40            :
  41            : "cc");
  42
  43         return val;
  44 }
  45
  46 static int cpu_is_u8500v11(void)
  47 {
  48         return read_asicid() == ASICID_DB8500V11;
  49 }
  50
  51 static int cpu_is_u8500v2(void)
  52 {
  53         return read_cpuid() == CPUID_DB8500V2;
  54 }
  55
  56 static unsigned int read_asicid(void)
  57 {
  58         unsigned int *address;
  59
  60         if (cpu_is_u8500v2())
  61                 address = (void *) U8500_ASIC_ID_LOC_V2;
  62         else
  63                 address = (void *) U8500_ASIC_ID_LOC_ED_V1;
  64
  65         return readl(address);
  66 }
  67
  68 void cpu_cache_initialization(void)
  69 {
  70         unsigned int value;
  71         /* invalidate all cache entries */
  72         writel(0xFFFF, CACHE_INVAL_BY_WAY);
  73
  74         /* ways are set to '0' when they are totally
  75          * cleaned and invalidated
  76          */
  77         do {
  78                 value = readl(CACHE_INVAL_BY_WAY);
  79         } while (value & 0xFF);
  80
  81         /* Invalidate register 9 D and I lockdown */
  82         writel(0xFF, CACHE_LOCKDOWN_BY_D);
  83         writel(0xFF, CACHE_LOCKDOWN_BY_I);
  84 }
  85
  86 #ifdef CONFIG_ARCH_CPU_INIT
  87 /*
  88  * SOC specific cpu init
  89  */
  90 int arch_cpu_init(void)
  91 {
  92         db8500_prcmu_init();
  93         db8500_clocks_init();
  94
  95         return 0;
  96 }
  97 #endif /* CONFIG_ARCH_CPU_INIT */
  98
  99 #ifdef CONFIG_MMC
 100
 101 int u8500_mmc_power_init(void)
 102 {
 103         int ret;
 104         int enable, voltage;
 105         int ab8500_revision;
 106
 107         if (!cpu_is_u8500v11() && !cpu_is_u8500v2())
 108                 return 0;
 109
 110         /* Get AB8500 revision */
 111         ret = ab8500_read(AB8500_MISC, AB8500_REV_REG);
 112         if (ret < 0)
 113                 goto out;
 114
 115         ab8500_revision = ret;
 116
 117         /*
 118          * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD
 119          * card to work.  This is done by enabling the regulators in the AB8500
 120          * via PRCMU I2C transactions.
 121          *
 122          * This code is derived from the handling of AB8500_LDO_VAUX3 in
 123          * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux.
 124          *
 125          * Turn off and delay is required to have it work across soft reboots.
 126          */
 127
 128         /* Turn off (read-modify-write) */
 129         ret = ab8500_read(AB8500_REGU_CTRL2,
 130                                 AB8500_REGU_VRF1VAUX3_REGU_REG);
 131         if (ret < 0)
 132                 goto out;
 133
 134         enable = ret;
 135
 136         /* Turn off */
 137         ret = ab8500_write(AB8500_REGU_CTRL2,
 138                         AB8500_REGU_VRF1VAUX3_REGU_REG,
 139                         enable & ~LDO_VAUX3_ENABLE_MASK);
 140         if (ret < 0)
 141                 goto out;
 142
 143         udelay(10 * 1000);
 144
 145         /* Set the voltage to 2.91 V or 2.9 V without overriding VRF1 value */
 146         ret = ab8500_read(AB8500_REGU_CTRL2,
 147                         AB8500_REGU_VRF1VAUX3_SEL_REG);
 148         if (ret < 0)
 149                 goto out;
 150
 151         voltage = ret;
 152
 153         if (ab8500_revision < 0x20) {
 154                 voltage &= ~LDO_VAUX3_SEL_MASK;
 155                 voltage |= LDO_VAUX3_SEL_2V9;
 156         } else {
 157                 voltage &= ~LDO_VAUX3_V2_SEL_MASK;
 158                 voltage |= LDO_VAUX3_V2_SEL_2V91;
 159         }
 160
 161         ret = ab8500_write(AB8500_REGU_CTRL2,
 162                         AB8500_REGU_VRF1VAUX3_SEL_REG, voltage);
 163         if (ret < 0)
 164                 goto out;
 165
 166         /* Turn on the supply */
 167         enable &= ~LDO_VAUX3_ENABLE_MASK;
 168         enable |= LDO_VAUX3_ENABLE_VAL;
 169
 170         ret = ab8500_write(AB8500_REGU_CTRL2,
 171                         AB8500_REGU_VRF1VAUX3_REGU_REG, enable);
 172
 173 out:
 174         return ret;
 175 }
 176 #endif /* CONFIG_MMC */