]>
git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c
2 * Copyright (C) 2011-2014 Panasonic Corporation
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/umc-regs.h>
11 static inline void umc_start_ssif(void __iomem
*ssif_base
)
13 writel(0x00000000, ssif_base
+ 0x0000b004);
14 writel(0xffffffff, ssif_base
+ 0x0000c004);
15 writel(0x000fffcf, ssif_base
+ 0x0000c008);
16 writel(0x00000001, ssif_base
+ 0x0000b000);
17 writel(0x00000001, ssif_base
+ 0x0000c000);
18 writel(0x03010101, ssif_base
+ UMC_MDMCHSEL
);
19 writel(0x03010100, ssif_base
+ UMC_DMDCHSEL
);
21 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_FETCH
);
22 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMQUE0
);
23 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMWC0
);
24 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMRC0
);
25 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMQUE1
);
26 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMWC1
);
27 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMRC1
);
28 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_WC
);
29 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_RC
);
30 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_DST
);
32 writel(0x00000001, ssif_base
+ UMC_CPURST
);
33 writel(0x00000001, ssif_base
+ UMC_IDSRST
);
34 writel(0x00000001, ssif_base
+ UMC_IXMRST
);
35 writel(0x00000001, ssif_base
+ UMC_MDMRST
);
36 writel(0x00000001, ssif_base
+ UMC_MDDRST
);
37 writel(0x00000001, ssif_base
+ UMC_SIORST
);
38 writel(0x00000001, ssif_base
+ UMC_VIORST
);
39 writel(0x00000001, ssif_base
+ UMC_FRCRST
);
40 writel(0x00000001, ssif_base
+ UMC_RGLRST
);
41 writel(0x00000001, ssif_base
+ UMC_AIORST
);
42 writel(0x00000001, ssif_base
+ UMC_DMDRST
);
45 void umc_dramcont_init(void __iomem
*dramcont
, void __iomem
*ca_base
,
48 #ifdef CONFIG_DDR_STANDARD
49 writel(0x55990b11, dramcont
+ UMC_CMDCTLA
);
50 writel(0x16958944, dramcont
+ UMC_CMDCTLB
);
52 writel(0x45990b11, dramcont
+ UMC_CMDCTLA
);
53 writel(0x16958924, dramcont
+ UMC_CMDCTLB
);
56 writel(0x5101046A, dramcont
+ UMC_INITCTLA
);
59 writel(0x27028B0A, dramcont
+ UMC_INITCTLB
);
61 writel(0x38028B0A, dramcont
+ UMC_INITCTLB
);
63 writel(0x00FF00FF, dramcont
+ UMC_INITCTLC
);
64 writel(0x00000b51, dramcont
+ UMC_DRMMR0
);
65 writel(0x00000006, dramcont
+ UMC_DRMMR1
);
66 writel(0x00000290, dramcont
+ UMC_DRMMR2
);
68 #ifdef CONFIG_DDR_STANDARD
69 writel(0x00000000, dramcont
+ UMC_DRMMR3
);
71 writel(0x00000800, dramcont
+ UMC_DRMMR3
);
75 writel(0x00240512, dramcont
+ UMC_SPCCTLA
);
77 writel(0x00350512, dramcont
+ UMC_SPCCTLA
);
79 writel(0x00ff0006, dramcont
+ UMC_SPCCTLB
);
80 writel(0x000a00ac, dramcont
+ UMC_RDATACTL_D0
);
81 writel(0x04060806, dramcont
+ UMC_WDATACTL_D0
);
82 writel(0x04a02000, dramcont
+ UMC_DATASET
);
83 writel(0x00000000, ca_base
+ 0x2300);
84 writel(0x00400020, dramcont
+ UMC_DCCGCTL
);
85 writel(0x00000003, dramcont
+ 0x7000);
86 writel(0x0000004f, dramcont
+ 0x8000);
87 writel(0x000000c3, dramcont
+ 0x8004);
88 writel(0x00000077, dramcont
+ 0x8008);
89 writel(0x0000003b, dramcont
+ UMC_DICGCTLA
);
90 writel(0x020a0808, dramcont
+ UMC_DICGCTLB
);
91 writel(0x00000004, dramcont
+ UMC_FLOWCTLG
);
92 writel(0x80000201, ca_base
+ 0xc20);
93 writel(0x0801e01e, dramcont
+ UMC_FLOWCTLA
);
94 writel(0x00200000, dramcont
+ UMC_FLOWCTLB
);
95 writel(0x00004444, dramcont
+ UMC_FLOWCTLC
);
96 writel(0x200a0a00, dramcont
+ UMC_SPCSETB
);
97 writel(0x00000000, dramcont
+ UMC_SPCSETD
);
98 writel(0x00000520, dramcont
+ UMC_DFICUPDCTLA
);
101 static inline int umc_init_sub(int freq
, int size_ch0
, int size_ch1
)
103 void __iomem
*ssif_base
= (void __iomem
*)UMC_SSIF_BASE
;
104 void __iomem
*ca_base0
= (void __iomem
*)UMC_CA_BASE(0);
105 void __iomem
*ca_base1
= (void __iomem
*)UMC_CA_BASE(1);
106 void __iomem
*dramcont0
= (void __iomem
*)UMC_DRAMCONT_BASE(0);
107 void __iomem
*dramcont1
= (void __iomem
*)UMC_DRAMCONT_BASE(1);
109 umc_dram_init_start(dramcont0
);
110 umc_dram_init_start(dramcont1
);
111 umc_dram_init_poll(dramcont0
);
112 umc_dram_init_poll(dramcont1
);
114 writel(0x00000101, dramcont0
+ UMC_DIOCTLA
);
116 writel(0x00000101, dramcont1
+ UMC_DIOCTLA
);
118 umc_dramcont_init(dramcont0
, ca_base0
, size_ch0
, freq
);
119 umc_dramcont_init(dramcont1
, ca_base1
, size_ch1
, freq
);
121 umc_start_ssif(ssif_base
);
128 return umc_init_sub(CONFIG_DDR_FREQ
, CONFIG_SDRAM0_SIZE
/ 0x08000000,
129 CONFIG_SDRAM1_SIZE
/ 0x08000000);
132 #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
133 (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
134 CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
137 #error Unsupported DDR configuration.