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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/cpu/armv7/zynq/slcr.c
2 * Copyright (c) 2013 Xilinx Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/hardware.h>
28 #define SLCR_LOCK_MAGIC 0x767B
29 #define SLCR_UNLOCK_MAGIC 0xDF0D
31 #define SLCR_IDCODE_MASK 0x1F000
32 #define SLCR_IDCODE_SHIFT 12
34 static int slcr_lock
= 1; /* 1 means locked, 0 means unlocked */
36 void zynq_slcr_lock(void)
39 writel(SLCR_LOCK_MAGIC
, &slcr_base
->slcr_lock
);
42 void zynq_slcr_unlock(void)
45 writel(SLCR_UNLOCK_MAGIC
, &slcr_base
->slcr_unlock
);
48 /* Reset the entire system */
49 void zynq_slcr_cpu_reset(void)
52 * Unlock the SLCR then reset the system.
53 * Note that this seems to require raw i/o
54 * functions or there's a lockup?
59 * Clear 0x0F000000 bits of reboot status register to workaround
60 * the FSBL not loading the bitstream after soft-reboot
61 * This is a temporary solution until we know more.
63 clrbits_le32(&slcr_base
->reboot_status
, 0xF000000);
65 writel(1, &slcr_base
->pss_rst_ctrl
);
68 /* Setup clk for network */
69 void zynq_slcr_gem_clk_setup(u32 gem_id
, u32 rclk
, u32 clk
)
74 printf("Non existing GEM id %d\n", gem_id
);
79 /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
80 writel(clk
, &slcr_base
->gem1_clk_ctrl
);
81 /* Configure GEM_RCLK_CTRL */
82 writel(rclk
, &slcr_base
->gem1_rclk_ctrl
);
84 /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
85 writel(clk
, &slcr_base
->gem0_clk_ctrl
);
86 /* Configure GEM_RCLK_CTRL */
87 writel(rclk
, &slcr_base
->gem0_rclk_ctrl
);
94 void zynq_slcr_devcfg_disable(void)
98 /* Disable AXI interface */
99 writel(0xFFFFFFFF, &slcr_base
->fpga_rst_ctrl
);
101 /* Set Level Shifters DT618760 */
102 writel(0xA, &slcr_base
->lvl_shftr_en
);
107 void zynq_slcr_devcfg_enable(void)
111 /* Set Level Shifters DT618760 */
112 writel(0xF, &slcr_base
->lvl_shftr_en
);
114 /* Disable AXI interface */
115 writel(0x0, &slcr_base
->fpga_rst_ctrl
);
120 u32
zynq_slcr_get_idcode(void)
122 return (readl(&slcr_base
->pss_idcode
) & SLCR_IDCODE_MASK
) >>