arch/arm/cpu/armv8/cache_v8.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013
   4  * David Feng <fenghua@phytium.com.cn>
   5  *
   6  * (C) Copyright 2016
   7  * Alexander Graf <agraf@suse.de>
   8  */
   9
  10 #include <common.h>
  11 #include <cpu_func.h>
  12 #include <hang.h>
  13 #include <log.h>
  14 #include <asm/cache.h>
  15 #include <asm/global_data.h>
  16 #include <asm/system.h>
  17 #include <asm/armv8/mmu.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  22
  23 /*
  24  *  With 4k page granule, a virtual address is split into 4 lookup parts
  25  *  spanning 9 bits each:
  26  *
  27  *    _______________________________________________
  28  *   |       |       |       |       |       |       |
  29  *   |   0   |  Lv0  |  Lv1  |  Lv2  |  Lv3  |  off  |
  30  *   |_______|_______|_______|_______|_______|_______|
  31  *     63-48   47-39   38-30   29-21   20-12   11-00
  32  *
  33  *             mask        page size
  34  *
  35  *    Lv0: FF8000000000       --
  36  *    Lv1:   7FC0000000       1G
  37  *    Lv2:     3FE00000       2M
  38  *    Lv3:       1FF000       4K
  39  *    off:          FFF
  40  */
  41
  42 static int get_effective_el(void)
  43 {
  44         int el = current_el();
  45
  46         if (el == 2) {
  47                 u64 hcr_el2;
  48
  49                 /*
  50                  * If we are using the EL2&0 translation regime, the TCR_EL2
  51                  * looks like the EL1 version, even though we are in EL2.
  52                  */
  53                 __asm__ ("mrs %0, HCR_EL2\n" : "=r" (hcr_el2));
  54                 if (hcr_el2 & BIT(HCR_EL2_E2H_BIT))
  55                         return 1;
  56         }
  57
  58         return el;
  59 }
  60
  61 u64 get_tcr(u64 *pips, u64 *pva_bits)
  62 {
  63         int el = get_effective_el();
  64         u64 max_addr = 0;
  65         u64 ips, va_bits;
  66         u64 tcr;
  67         int i;
  68
  69         /* Find the largest address we need to support */
  70         for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
  71                 max_addr = max(max_addr, mem_map[i].virt + mem_map[i].size);
  72
  73         /* Calculate the maximum physical (and thus virtual) address */
  74         if (max_addr > (1ULL << 44)) {
  75                 ips = 5;
  76                 va_bits = 48;
  77         } else  if (max_addr > (1ULL << 42)) {
  78                 ips = 4;
  79                 va_bits = 44;
  80         } else  if (max_addr > (1ULL << 40)) {
  81                 ips = 3;
  82                 va_bits = 42;
  83         } else  if (max_addr > (1ULL << 36)) {
  84                 ips = 2;
  85                 va_bits = 40;
  86         } else  if (max_addr > (1ULL << 32)) {
  87                 ips = 1;
  88                 va_bits = 36;
  89         } else {
  90                 ips = 0;
  91                 va_bits = 32;
  92         }
  93
  94         if (el == 1) {
  95                 tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
  96         } else if (el == 2) {
  97                 tcr = TCR_EL2_RSVD | (ips << 16);
  98         } else {
  99                 tcr = TCR_EL3_RSVD | (ips << 16);
 100         }
 101
 102         /* PTWs cacheable, inner/outer WBWA and inner shareable */
 103         tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
 104         tcr |= TCR_T0SZ(va_bits);
 105
 106         if (pips)
 107                 *pips = ips;
 108         if (pva_bits)
 109                 *pva_bits = va_bits;
 110
 111         return tcr;
 112 }
 113
 114 #define MAX_PTE_ENTRIES 512
 115
 116 static int pte_type(u64 *pte)
 117 {
 118         return *pte & PTE_TYPE_MASK;
 119 }
 120
 121 /* Returns the LSB number for a PTE on level <level> */
 122 static int level2shift(int level)
 123 {
 124         /* Page is 12 bits wide, every level translates 9 bits */
 125         return (12 + 9 * (3 - level));
 126 }
 127
 128 static u64 *find_pte(u64 addr, int level)
 129 {
 130         int start_level = 0;
 131         u64 *pte;
 132         u64 idx;
 133         u64 va_bits;
 134         int i;
 135
 136         debug("addr=%llx level=%d\n", addr, level);
 137
 138         get_tcr(NULL, &va_bits);
 139         if (va_bits < 39)
 140                 start_level = 1;
 141
 142         if (level < start_level)
 143                 return NULL;
 144
 145         /* Walk through all page table levels to find our PTE */
 146         pte = (u64*)gd->arch.tlb_addr;
 147         for (i = start_level; i < 4; i++) {
 148                 idx = (addr >> level2shift(i)) & 0x1FF;
 149                 pte += idx;
 150                 debug("idx=%llx PTE %p at level %d: %llx\n", idx, pte, i, *pte);
 151
 152                 /* Found it */
 153                 if (i == level)
 154                         return pte;
 155                 /* PTE is no table (either invalid or block), can't traverse */
 156                 if (pte_type(pte) != PTE_TYPE_TABLE)
 157                         return NULL;
 158                 /* Off to the next level */
 159                 pte = (u64*)(*pte & 0x0000fffffffff000ULL);
 160         }
 161
 162         /* Should never reach here */
 163         return NULL;
 164 }
 165
 166 /* Returns and creates a new full table (512 entries) */
 167 static u64 *create_table(void)
 168 {
 169         u64 *new_table = (u64*)gd->arch.tlb_fillptr;
 170         u64 pt_len = MAX_PTE_ENTRIES * sizeof(u64);
 171
 172         /* Allocate MAX_PTE_ENTRIES pte entries */
 173         gd->arch.tlb_fillptr += pt_len;
 174
 175         if (gd->arch.tlb_fillptr - gd->arch.tlb_addr > gd->arch.tlb_size)
 176                 panic("Insufficient RAM for page table: 0x%lx > 0x%lx. "
 177                       "Please increase the size in get_page_table_size()",
 178                         gd->arch.tlb_fillptr - gd->arch.tlb_addr,
 179                         gd->arch.tlb_size);
 180
 181         /* Mark all entries as invalid */
 182         memset(new_table, 0, pt_len);
 183
 184         return new_table;
 185 }
 186
 187 static void set_pte_table(u64 *pte, u64 *table)
 188 {
 189         /* Point *pte to the new table */
 190         debug("Setting %p to addr=%p\n", pte, table);
 191         *pte = PTE_TYPE_TABLE | (ulong)table;
 192 }
 193
 194 /* Splits a block PTE into table with subpages spanning the old block */
 195 static void split_block(u64 *pte, int level)
 196 {
 197         u64 old_pte = *pte;
 198         u64 *new_table;
 199         u64 i = 0;
 200         /* level describes the parent level, we need the child ones */
 201         int levelshift = level2shift(level + 1);
 202
 203         if (pte_type(pte) != PTE_TYPE_BLOCK)
 204                 panic("PTE %p (%llx) is not a block. Some driver code wants to "
 205                       "modify dcache settings for an range not covered in "
 206                       "mem_map.", pte, old_pte);
 207
 208         new_table = create_table();
 209         debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table);
 210
 211         for (i = 0; i < MAX_PTE_ENTRIES; i++) {
 212                 new_table[i] = old_pte | (i << levelshift);
 213
 214                 /* Level 3 block PTEs have the table type */
 215                 if ((level + 1) == 3)
 216                         new_table[i] |= PTE_TYPE_TABLE;
 217
 218                 debug("Setting new_table[%lld] = %llx\n", i, new_table[i]);
 219         }
 220
 221         /* Set the new table into effect */
 222         set_pte_table(pte, new_table);
 223 }
 224
 225 /* Add one mm_region map entry to the page tables */
 226 static void add_map(struct mm_region *map)
 227 {
 228         u64 *pte;
 229         u64 virt = map->virt;
 230         u64 phys = map->phys;
 231         u64 size = map->size;
 232         u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
 233         u64 blocksize;
 234         int level;
 235         u64 *new_table;
 236
 237         while (size) {
 238                 pte = find_pte(virt, 0);
 239                 if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) {
 240                         debug("Creating table for virt 0x%llx\n", virt);
 241                         new_table = create_table();
 242                         set_pte_table(pte, new_table);
 243                 }
 244
 245                 for (level = 1; level < 4; level++) {
 246                         pte = find_pte(virt, level);
 247                         if (!pte)
 248                                 panic("pte not found\n");
 249
 250                         blocksize = 1ULL << level2shift(level);
 251                         debug("Checking if pte fits for virt=%llx size=%llx blocksize=%llx\n",
 252                               virt, size, blocksize);
 253                         if (size >= blocksize && !(virt & (blocksize - 1))) {
 254                                 /* Page fits, create block PTE */
 255                                 debug("Setting PTE %p to block virt=%llx\n",
 256                                       pte, virt);
 257                                 if (level == 3)
 258                                         *pte = phys | attrs | PTE_TYPE_PAGE;
 259                                 else
 260                                         *pte = phys | attrs;
 261                                 virt += blocksize;
 262                                 phys += blocksize;
 263                                 size -= blocksize;
 264                                 break;
 265                         } else if (pte_type(pte) == PTE_TYPE_FAULT) {
 266                                 /* Page doesn't fit, create subpages */
 267                                 debug("Creating subtable for virt 0x%llx blksize=%llx\n",
 268                                       virt, blocksize);
 269                                 new_table = create_table();
 270                                 set_pte_table(pte, new_table);
 271                         } else if (pte_type(pte) == PTE_TYPE_BLOCK) {
 272                                 debug("Split block into subtable for virt 0x%llx blksize=0x%llx\n",
 273                                       virt, blocksize);
 274                                 split_block(pte, level);
 275                         }
 276                 }
 277         }
 278 }
 279
 280 enum pte_type {
 281         PTE_INVAL,
 282         PTE_BLOCK,
 283         PTE_LEVEL,
 284 };
 285
 286 /*
 287  * This is a recursively called function to count the number of
 288  * page tables we need to cover a particular PTE range. If you
 289  * call this with level = -1 you basically get the full 48 bit
 290  * coverage.
 291  */
 292 static int count_required_pts(u64 addr, int level, u64 maxaddr)
 293 {
 294         int levelshift = level2shift(level);
 295         u64 levelsize = 1ULL << levelshift;
 296         u64 levelmask = levelsize - 1;
 297         u64 levelend = addr + levelsize;
 298         int r = 0;
 299         int i;
 300         enum pte_type pte_type = PTE_INVAL;
 301
 302         for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
 303                 struct mm_region *map = &mem_map[i];
 304                 u64 start = map->virt;
 305                 u64 end = start + map->size;
 306
 307                 /* Check if the PTE would overlap with the map */
 308                 if (max(addr, start) <= min(levelend, end)) {
 309                         start = max(addr, start);
 310                         end = min(levelend, end);
 311
 312                         /* We need a sub-pt for this level */
 313                         if ((start & levelmask) || (end & levelmask)) {
 314                                 pte_type = PTE_LEVEL;
 315                                 break;
 316                         }
 317
 318                         /* Lv0 can not do block PTEs, so do levels here too */
 319                         if (level <= 0) {
 320                                 pte_type = PTE_LEVEL;
 321                                 break;
 322                         }
 323
 324                         /* PTE is active, but fits into a block */
 325                         pte_type = PTE_BLOCK;
 326                 }
 327         }
 328
 329         /*
 330          * Block PTEs at this level are already covered by the parent page
 331          * table, so we only need to count sub page tables.
 332          */
 333         if (pte_type == PTE_LEVEL) {
 334                 int sublevel = level + 1;
 335                 u64 sublevelsize = 1ULL << level2shift(sublevel);
 336
 337                 /* Account for the new sub page table ... */
 338                 r = 1;
 339
 340                 /* ... and for all child page tables that one might have */
 341                 for (i = 0; i < MAX_PTE_ENTRIES; i++) {
 342                         r += count_required_pts(addr, sublevel, maxaddr);
 343                         addr += sublevelsize;
 344
 345                         if (addr >= maxaddr) {
 346                                 /*
 347                                  * We reached the end of address space, no need
 348                                  * to look any further.
 349                                  */
 350                                 break;
 351                         }
 352                 }
 353         }
 354
 355         return r;
 356 }
 357
 358 /* Returns the estimated required size of all page tables */
 359 __weak u64 get_page_table_size(void)
 360 {
 361         u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
 362         u64 size = 0;
 363         u64 va_bits;
 364         int start_level = 0;
 365
 366         get_tcr(NULL, &va_bits);
 367         if (va_bits < 39)
 368                 start_level = 1;
 369
 370         /* Account for all page tables we would need to cover our memory map */
 371         size = one_pt * count_required_pts(0, start_level - 1, 1ULL << va_bits);
 372
 373         /*
 374          * We need to duplicate our page table once to have an emergency pt to
 375          * resort to when splitting page tables later on
 376          */
 377         size *= 2;
 378
 379         /*
 380          * We may need to split page tables later on if dcache settings change,
 381          * so reserve up to 4 (random pick) page tables for that.
 382          */
 383         size += one_pt * 4;
 384
 385         return size;
 386 }
 387
 388 void setup_pgtables(void)
 389 {
 390         int i;
 391
 392         if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr)
 393                 panic("Page table pointer not setup.");
 394
 395         /*
 396          * Allocate the first level we're on with invalidate entries.
 397          * If the starting level is 0 (va_bits >= 39), then this is our
 398          * Lv0 page table, otherwise it's the entry Lv1 page table.
 399          */
 400         create_table();
 401
 402         /* Now add all MMU table entries one after another to the table */
 403         for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
 404                 add_map(&mem_map[i]);
 405 }
 406
 407 static void setup_all_pgtables(void)
 408 {
 409         u64 tlb_addr = gd->arch.tlb_addr;
 410         u64 tlb_size = gd->arch.tlb_size;
 411
 412         /* Reset the fill ptr */
 413         gd->arch.tlb_fillptr = tlb_addr;
 414
 415         /* Create normal system page tables */
 416         setup_pgtables();
 417
 418         /* Create emergency page tables */
 419         gd->arch.tlb_size -= (uintptr_t)gd->arch.tlb_fillptr -
 420                              (uintptr_t)gd->arch.tlb_addr;
 421         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 422         setup_pgtables();
 423         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 424         gd->arch.tlb_addr = tlb_addr;
 425         gd->arch.tlb_size = tlb_size;
 426 }
 427
 428 /* to activate the MMU we need to set up virtual memory */
 429 __weak void mmu_setup(void)
 430 {
 431         int el;
 432
 433         /* Set up page tables only once */
 434         if (!gd->arch.tlb_fillptr)
 435                 setup_all_pgtables();
 436
 437         el = current_el();
 438         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
 439                           MEMORY_ATTRIBUTES);
 440
 441         /* enable the mmu */
 442         set_sctlr(get_sctlr() | CR_M);
 443 }
 444
 445 /*
 446  * Performs a invalidation of the entire data cache at all levels
 447  */
 448 void invalidate_dcache_all(void)
 449 {
 450         __asm_invalidate_dcache_all();
 451         __asm_invalidate_l3_dcache();
 452 }
 453
 454 /*
 455  * Performs a clean & invalidation of the entire data cache at all levels.
 456  * This function needs to be inline to avoid using stack.
 457  * __asm_flush_l3_dcache return status of timeout
 458  */
 459 inline void flush_dcache_all(void)
 460 {
 461         int ret;
 462
 463         __asm_flush_dcache_all();
 464         ret = __asm_flush_l3_dcache();
 465         if (ret)
 466                 debug("flushing dcache returns 0x%x\n", ret);
 467         else
 468                 debug("flushing dcache successfully.\n");
 469 }
 470
 471 #ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
 472 /*
 473  * Invalidates range in all levels of D-cache/unified cache
 474  */
 475 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 476 {
 477         __asm_invalidate_dcache_range(start, stop);
 478 }
 479
 480 /*
 481  * Flush range(clean & invalidate) from all levels of D-cache/unified cache
 482  */
 483 void flush_dcache_range(unsigned long start, unsigned long stop)
 484 {
 485         __asm_flush_dcache_range(start, stop);
 486 }
 487 #else
 488 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 489 {
 490 }
 491
 492 void flush_dcache_range(unsigned long start, unsigned long stop)
 493 {
 494 }
 495 #endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
 496
 497 void dcache_enable(void)
 498 {
 499         /* The data cache is not active unless the mmu is enabled */
 500         if (!(get_sctlr() & CR_M)) {
 501                 invalidate_dcache_all();
 502                 __asm_invalidate_tlb_all();
 503                 mmu_setup();
 504         }
 505
 506         /* Set up page tables only once (it is done also by mmu_setup()) */
 507         if (!gd->arch.tlb_fillptr)
 508                 setup_all_pgtables();
 509
 510         set_sctlr(get_sctlr() | CR_C);
 511 }
 512
 513 void dcache_disable(void)
 514 {
 515         uint32_t sctlr;
 516
 517         sctlr = get_sctlr();
 518
 519         /* if cache isn't enabled no need to disable */
 520         if (!(sctlr & CR_C))
 521                 return;
 522
 523         set_sctlr(sctlr & ~(CR_C|CR_M));
 524
 525         flush_dcache_all();
 526         __asm_invalidate_tlb_all();
 527 }
 528
 529 int dcache_status(void)
 530 {
 531         return (get_sctlr() & CR_C) != 0;
 532 }
 533
 534 u64 *__weak arch_get_page_table(void) {
 535         puts("No page table offset defined\n");
 536
 537         return NULL;
 538 }
 539
 540 static bool is_aligned(u64 addr, u64 size, u64 align)
 541 {
 542         return !(addr & (align - 1)) && !(size & (align - 1));
 543 }
 544
 545 /* Use flag to indicate if attrs has more than d-cache attributes */
 546 static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
 547 {
 548         int levelshift = level2shift(level);
 549         u64 levelsize = 1ULL << levelshift;
 550         u64 *pte = find_pte(start, level);
 551
 552         /* Can we can just modify the current level block PTE? */
 553         if (is_aligned(start, size, levelsize)) {
 554                 if (flag) {
 555                         *pte &= ~PMD_ATTRMASK;
 556                         *pte |= attrs & PMD_ATTRMASK;
 557                 } else {
 558                         *pte &= ~PMD_ATTRINDX_MASK;
 559                         *pte |= attrs & PMD_ATTRINDX_MASK;
 560                 }
 561                 debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
 562
 563                 return levelsize;
 564         }
 565
 566         /* Unaligned or doesn't fit, maybe split block into table */
 567         debug("addr=%llx level=%d pte=%p (%llx)\n", start, level, pte, *pte);
 568
 569         /* Maybe we need to split the block into a table */
 570         if (pte_type(pte) == PTE_TYPE_BLOCK)
 571                 split_block(pte, level);
 572
 573         /* And then double-check it became a table or already is one */
 574         if (pte_type(pte) != PTE_TYPE_TABLE)
 575                 panic("PTE %p (%llx) for addr=%llx should be a table",
 576                       pte, *pte, start);
 577
 578         /* Roll on to the next page table level */
 579         return 0;
 580 }
 581
 582 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 583                                      enum dcache_option option)
 584 {
 585         u64 attrs = PMD_ATTRINDX(option >> 2);
 586         u64 real_start = start;
 587         u64 real_size = size;
 588
 589         debug("start=%lx size=%lx\n", (ulong)start, (ulong)size);
 590
 591         if (!gd->arch.tlb_emerg)
 592                 panic("Emergency page table not setup.");
 593
 594         /*
 595          * We can not modify page tables that we're currently running on,
 596          * so we first need to switch to the "emergency" page tables where
 597          * we can safely modify our primary page tables and then switch back
 598          */
 599         __asm_switch_ttbr(gd->arch.tlb_emerg);
 600
 601         /*
 602          * Loop through the address range until we find a page granule that fits
 603          * our alignment constraints, then set it to the new cache attributes
 604          */
 605         while (size > 0) {
 606                 int level;
 607                 u64 r;
 608
 609                 for (level = 1; level < 4; level++) {
 610                         /* Set d-cache attributes only */
 611                         r = set_one_region(start, size, attrs, false, level);
 612                         if (r) {
 613                                 /* PTE successfully replaced */
 614                                 size -= r;
 615                                 start += r;
 616                                 break;
 617                         }
 618                 }
 619
 620         }
 621
 622         /* We're done modifying page tables, switch back to our primary ones */
 623         __asm_switch_ttbr(gd->arch.tlb_addr);
 624
 625         /*
 626          * Make sure there's nothing stale in dcache for a region that might
 627          * have caches off now
 628          */
 629         flush_dcache_range(real_start, real_start + real_size);
 630 }
 631
 632 /*
 633  * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
 634  * The procecess is break-before-make. The target region will be marked as
 635  * invalid during the process of changing.
 636  */
 637 void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
 638 {
 639         int level;
 640         u64 r, size, start;
 641
 642         start = addr;
 643         size = siz;
 644         /*
 645          * Loop through the address range until we find a page granule that fits
 646          * our alignment constraints, then set it to "invalid".
 647          */
 648         while (size > 0) {
 649                 for (level = 1; level < 4; level++) {
 650                         /* Set PTE to fault */
 651                         r = set_one_region(start, size, PTE_TYPE_FAULT, true,
 652                                            level);
 653                         if (r) {
 654                                 /* PTE successfully invalidated */
 655                                 size -= r;
 656                                 start += r;
 657                                 break;
 658                         }
 659                 }
 660         }
 661
 662         flush_dcache_range(gd->arch.tlb_addr,
 663                            gd->arch.tlb_addr + gd->arch.tlb_size);
 664         __asm_invalidate_tlb_all();
 665
 666         /*
 667          * Loop through the address range until we find a page granule that fits
 668          * our alignment constraints, then set it to the new cache attributes
 669          */
 670         start = addr;
 671         size = siz;
 672         while (size > 0) {
 673                 for (level = 1; level < 4; level++) {
 674                         /* Set PTE to new attributes */
 675                         r = set_one_region(start, size, attrs, true, level);
 676                         if (r) {
 677                                 /* PTE successfully updated */
 678                                 size -= r;
 679                                 start += r;
 680                                 break;
 681                         }
 682                 }
 683         }
 684         flush_dcache_range(gd->arch.tlb_addr,
 685                            gd->arch.tlb_addr + gd->arch.tlb_size);
 686         __asm_invalidate_tlb_all();
 687 }
 688
 689 #else   /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 690
 691 /*
 692  * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
 693  * running however really wants to have dcache and the MMU active. Check that
 694  * everything is sane and give the developer a hint if it isn't.
 695  */
 696 #ifndef CONFIG_SPL_BUILD
 697 #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
 698 #endif
 699
 700 void invalidate_dcache_all(void)
 701 {
 702 }
 703
 704 void flush_dcache_all(void)
 705 {
 706 }
 707
 708 void dcache_enable(void)
 709 {
 710 }
 711
 712 void dcache_disable(void)
 713 {
 714 }
 715
 716 int dcache_status(void)
 717 {
 718         return 0;
 719 }
 720
 721 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 722                                      enum dcache_option option)
 723 {
 724 }
 725
 726 #endif  /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 727
 728 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 729
 730 void icache_enable(void)
 731 {
 732         invalidate_icache_all();
 733         set_sctlr(get_sctlr() | CR_I);
 734 }
 735
 736 void icache_disable(void)
 737 {
 738         set_sctlr(get_sctlr() & ~CR_I);
 739 }
 740
 741 int icache_status(void)
 742 {
 743         return (get_sctlr() & CR_I) != 0;
 744 }
 745
 746 int mmu_status(void)
 747 {
 748         return (get_sctlr() & CR_M) != 0;
 749 }
 750
 751 void invalidate_icache_all(void)
 752 {
 753         __asm_invalidate_icache_all();
 754         __asm_invalidate_l3_icache();
 755 }
 756
 757 #else   /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
 758
 759 void icache_enable(void)
 760 {
 761 }
 762
 763 void icache_disable(void)
 764 {
 765 }
 766
 767 int icache_status(void)
 768 {
 769         return 0;
 770 }
 771
 772 int mmu_status(void)
 773 {
 774         return 0;
 775 }
 776
 777 void invalidate_icache_all(void)
 778 {
 779 }
 780
 781 #endif  /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
 782
 783 /*
 784  * Enable dCache & iCache, whether cache is actually enabled
 785  * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
 786  */
 787 void __weak enable_caches(void)
 788 {
 789         icache_enable();
 790         dcache_enable();
 791 }