arch/arm/cpu/armv8/fsl-layerscape/Kconfig

   1 config ARCH_LS1012A
   2         bool
   3         select FSL_LSCH2
   4         select SYS_FSL_DDR_BE
   5         select SYS_FSL_MMDC
   6         select SYS_FSL_ERRATUM_A010315
   7
   8 config ARCH_LS1043A
   9         bool
  10         select FSL_LSCH2
  11         select SYS_FSL_DDR_BE
  12         select SYS_FSL_DDR_VER_50
  13         select SYS_FSL_ERRATUM_A010315
  14         select SYS_FSL_ERRATUM_A010539
  15
  16 config ARCH_LS1046A
  17         bool
  18         select FSL_LSCH2
  19         select SYS_FSL_DDR_BE
  20         select SYS_FSL_DDR4
  21         select SYS_FSL_DDR_VER_50
  22         select SYS_FSL_ERRATUM_A010539
  23         select SYS_FSL_SRDS_2
  24
  25 config ARCH_LS2080A
  26         bool
  27         select FSL_LSCH3
  28         select SYS_FSL_DDR4
  29         select SYS_FSL_DDR_LE
  30         select SYS_FSL_DDR_VER_50
  31         select SYS_FSL_HAS_DP_DDR
  32         select SYS_FSL_HAS_SEC
  33         select SYS_FSL_SEC_COMPAT_5
  34         select SYS_FSL_SRDS_2
  35
  36 config FSL_LSCH2
  37         bool
  38         select SYS_FSL_HAS_SEC
  39         select SYS_FSL_SEC_COMPAT_5
  40         select SYS_FSL_SRDS_1
  41         select SYS_HAS_SERDES
  42
  43 config FSL_LSCH3
  44         bool
  45         select SYS_FSL_SRDS_1
  46         select SYS_HAS_SERDES
  47
  48 menu "Layerscape architecture"
  49         depends on FSL_LSCH2 || FSL_LSCH3
  50
  51 menu "Layerscape PPA"
  52 config FSL_LS_PPA
  53         bool "FSL Layerscape PPA firmware support"
  54         depends on !ARMV8_PSCI
  55         depends on ARCH_LS1043A || ARCH_LS1046A
  56         select FSL_PPA_ARMV8_PSCI
  57         help
  58           The FSL Primary Protected Application (PPA) is a software component
  59           which is loaded during boot stage, and then remains resident in RAM
  60           and runs in the TrustZone after boot.
  61           Say y to enable it.
  62
  63 config FSL_PPA_ARMV8_PSCI
  64         bool "PSCI implementation in PPA firmware"
  65         depends on FSL_LS_PPA
  66         help
  67           This config enables the ARMv8 PSCI implementation in PPA firmware.
  68           This is a private PSCI implementation and different from those
  69           implemented under the common ARMv8 PSCI framework.
  70 endmenu
  71
  72 config SYS_FSL_MMDC
  73         bool
  74
  75 config SYS_FSL_ERRATUM_A010315
  76         bool "Workaround for PCIe erratum A010315"
  77
  78 config SYS_FSL_ERRATUM_A010539
  79         bool "Workaround for PIN MUX erratum A010539"
  80
  81 config MAX_CPUS
  82         int "Maximum number of CPUs permitted for Layerscape"
  83         default 4 if ARCH_LS1043A
  84         default 4 if ARCH_LS1046A
  85         default 16 if ARCH_LS2080A
  86         default 1
  87         help
  88           Set this number to the maximum number of possible CPUs in the SoC.
  89           SoCs may have multiple clusters with each cluster may have multiple
  90           ports. If some ports are reserved but higher ports are used for
  91           cores, count the reserved ports. This will allocate enough memory
  92           in spin table to properly handle all cores.
  93
  94 config NUM_DDR_CONTROLLERS
  95         int "Maximum DDR controllers"
  96         default 3 if ARCH_LS2080A
  97         default 1
  98
  99 config SECURE_BOOT
 100         bool
 101         help
 102                 Enable Freescale Secure Boot feature
 103
 104 config QSPI_AHB_INIT
 105         bool "Init the QSPI AHB bus"
 106         help
 107           The default setting for QSPI AHB bus just support 3bytes addressing.
 108           But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
 109           bus for those flashes to support the full QSPI flash size.
 110
 111 config SYS_FSL_IFC_BANK_COUNT
 112         int "Maximum banks of Integrated flash controller"
 113         depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
 114         default 4 if ARCH_LS1043A
 115         default 4 if ARCH_LS1046A
 116         default 8 if ARCH_LS2080A
 117
 118 config SYS_FSL_HAS_DP_DDR
 119         bool
 120
 121 config SYS_FSL_SRDS_1
 122         bool
 123
 124 config SYS_FSL_SRDS_2
 125         bool
 126
 127 config SYS_HAS_SERDES
 128         bool
 129
 130 config SYS_FSL_DDR
 131         bool "Freescale DDR driver"
 132         help
 133           Select Freescale General DDR driver, shared between most Freescale
 134           PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
 135           based Layerscape SoCs (such as ls2080a).
 136
 137 config SYS_FSL_DDR_BE
 138         bool
 139         help
 140           Access DDR registers in big-endian.
 141
 142 config SYS_FSL_DDR_LE
 143         bool
 144         help
 145           Access DDR registers in little-endian.
 146
 147 config SYS_FSL_DDR_VER
 148         int
 149         default 50 if SYS_FSL_DDR_VER_50
 150
 151 config SYS_FSL_DDR_VER_50
 152         bool
 153
 154 config SYS_FSL_DDRC_ARM_GEN3
 155         bool
 156
 157 config SYS_FSL_DDRC_GEN4
 158         bool
 159
 160 config SYS_FSL_DDR3
 161         bool "Freescale DDR3 controller"
 162         depends on !SYS_FSL_DDR4
 163         select SYS_FSL_DDR
 164         select SYS_FSL_DDRC_ARM_GEN3
 165         help
 166           Enable Freescale DDR3 controller on ARM-based SoCs.
 167
 168 config SYS_FSL_DDR4
 169         bool "Freescale DDR4 controller"
 170         select SYS_FSL_DDR
 171         select SYS_FSL_DDRC_GEN4
 172         help
 173           Enable Freescale DDR4 controller.
 174
 175 endmenu