arch/arm/cpu/armv8/fsl-layerscape/Kconfig

   1 config ARCH_LS1012A
   2         bool
   3         select ARMV8_SET_SMPEN
   4         select FSL_LSCH2
   5         select SYS_FSL_DDR_BE
   6         select SYS_FSL_MMDC
   7         select SYS_FSL_ERRATUM_A010315
   8         select ARCH_EARLY_INIT_R
   9         select BOARD_EARLY_INIT_F
  10
  11 config ARCH_LS1043A
  12         bool
  13         select ARMV8_SET_SMPEN
  14         select FSL_LSCH2
  15         select SYS_FSL_DDR
  16         select SYS_FSL_DDR_BE
  17         select SYS_FSL_DDR_VER_50
  18         select SYS_FSL_ERRATUM_A008850
  19         select SYS_FSL_ERRATUM_A009660
  20         select SYS_FSL_ERRATUM_A009663
  21         select SYS_FSL_ERRATUM_A009929
  22         select SYS_FSL_ERRATUM_A009942
  23         select SYS_FSL_ERRATUM_A010315
  24         select SYS_FSL_ERRATUM_A010539
  25         select SYS_FSL_HAS_DDR3
  26         select SYS_FSL_HAS_DDR4
  27         select ARCH_EARLY_INIT_R
  28         select BOARD_EARLY_INIT_F
  29
  30 config ARCH_LS1046A
  31         bool
  32         select ARMV8_SET_SMPEN
  33         select FSL_LSCH2
  34         select SYS_FSL_DDR
  35         select SYS_FSL_DDR_BE
  36         select SYS_FSL_DDR_VER_50
  37         select SYS_FSL_ERRATUM_A008336
  38         select SYS_FSL_ERRATUM_A008511
  39         select SYS_FSL_ERRATUM_A008850
  40         select SYS_FSL_ERRATUM_A009801
  41         select SYS_FSL_ERRATUM_A009803
  42         select SYS_FSL_ERRATUM_A009942
  43         select SYS_FSL_ERRATUM_A010165
  44         select SYS_FSL_ERRATUM_A010539
  45         select SYS_FSL_HAS_DDR4
  46         select SYS_FSL_SRDS_2
  47         select ARCH_EARLY_INIT_R
  48         select BOARD_EARLY_INIT_F
  49
  50 config ARCH_LS2080A
  51         bool
  52         select ARMV8_SET_SMPEN
  53         select ARM_ERRATA_826974
  54         select ARM_ERRATA_828024
  55         select ARM_ERRATA_829520
  56         select ARM_ERRATA_833471
  57         select FSL_LSCH3
  58         select SYS_FSL_DDR
  59         select SYS_FSL_DDR_LE
  60         select SYS_FSL_DDR_VER_50
  61         select SYS_FSL_HAS_DP_DDR
  62         select SYS_FSL_HAS_SEC
  63         select SYS_FSL_HAS_DDR4
  64         select SYS_FSL_SEC_COMPAT_5
  65         select SYS_FSL_SEC_LE
  66         select SYS_FSL_SRDS_2
  67         select FSL_TZASC_1
  68         select FSL_TZASC_2
  69         select SYS_FSL_ERRATUM_A008336
  70         select SYS_FSL_ERRATUM_A008511
  71         select SYS_FSL_ERRATUM_A008514
  72         select SYS_FSL_ERRATUM_A008585
  73         select SYS_FSL_ERRATUM_A009635
  74         select SYS_FSL_ERRATUM_A009663
  75         select SYS_FSL_ERRATUM_A009801
  76         select SYS_FSL_ERRATUM_A009803
  77         select SYS_FSL_ERRATUM_A009942
  78         select SYS_FSL_ERRATUM_A010165
  79         select SYS_FSL_ERRATUM_A009203
  80         select ARCH_EARLY_INIT_R
  81         select BOARD_EARLY_INIT_F
  82
  83 config FSL_LSCH2
  84         bool
  85         select SYS_FSL_HAS_SEC
  86         select SYS_FSL_SEC_COMPAT_5
  87         select SYS_FSL_SEC_BE
  88         select SYS_FSL_SRDS_1
  89         select SYS_HAS_SERDES
  90
  91 config FSL_LSCH3
  92         bool
  93         select SYS_FSL_SRDS_1
  94         select SYS_HAS_SERDES
  95
  96 config FSL_MC_ENET
  97         bool "Management Complex network"
  98         depends on ARCH_LS2080A
  99         default y
 100         select RESV_RAM
 101         help
 102           Enable Management Complex (MC) network
 103
 104 menu "Layerscape architecture"
 105         depends on FSL_LSCH2 || FSL_LSCH3
 106
 107 config FSL_PCIE_COMPAT
 108         string "PCIe compatible of Kernel DT"
 109         depends on PCIE_LAYERSCAPE
 110         default "fsl,ls1012a-pcie" if ARCH_LS1012A
 111         default "fsl,ls1043a-pcie" if ARCH_LS1043A
 112         default "fsl,ls1046a-pcie" if ARCH_LS1046A
 113         default "fsl,ls2080a-pcie" if ARCH_LS2080A
 114         help
 115           This compatible is used to find pci controller node in Kernel DT
 116           to complete fixup.
 117
 118 config HAS_FEATURE_GIC64K_ALIGN
 119         bool
 120         default y if ARCH_LS1043A
 121
 122 config HAS_FEATURE_ENHANCED_MSI
 123         bool
 124         default y if ARCH_LS1043A
 125
 126 menu "Layerscape PPA"
 127 config FSL_LS_PPA
 128         bool "FSL Layerscape PPA firmware support"
 129         depends on !ARMV8_PSCI
 130         select ARMV8_SEC_FIRMWARE_SUPPORT
 131         select SEC_FIRMWARE_ARMV8_PSCI
 132         select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
 133         help
 134           The FSL Primary Protected Application (PPA) is a software component
 135           which is loaded during boot stage, and then remains resident in RAM
 136           and runs in the TrustZone after boot.
 137           Say y to enable it.
 138 choice
 139         prompt "FSL Layerscape PPA firmware loading-media select"
 140         depends on FSL_LS_PPA
 141         default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
 142         default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
 143         default SYS_LS_PPA_FW_IN_XIP
 144
 145 config SYS_LS_PPA_FW_IN_XIP
 146         bool "XIP"
 147         help
 148           Say Y here if the PPA firmware locate at XIP flash, such
 149           as NOR or QSPI flash.
 150
 151 config SYS_LS_PPA_FW_IN_MMC
 152         bool "eMMC or SD Card"
 153         help
 154           Say Y here if the PPA firmware locate at eMMC/SD card.
 155
 156 config SYS_LS_PPA_FW_IN_NAND
 157         bool "NAND"
 158         help
 159           Say Y here if the PPA firmware locate at NAND flash.
 160
 161 endchoice
 162
 163 config SYS_LS_PPA_FW_ADDR
 164         hex "Address of PPA firmware loading from"
 165         depends on FSL_LS_PPA
 166         default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
 167         default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
 168         default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
 169         default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
 170         default 0x400000 if SYS_LS_PPA_FW_IN_MMC
 171         default 0x400000 if SYS_LS_PPA_FW_IN_NAND
 172
 173         help
 174           If the PPA firmware locate at XIP flash, such as NOR or
 175           QSPI flash, this address is a directly memory-mapped.
 176           If it is in a serial accessed flash, such as NAND and SD
 177           card, it is a byte offset.
 178
 179 config SYS_LS_PPA_ESBC_ADDR
 180         hex "hdr address of PPA firmware loading from"
 181         depends on FSL_LS_PPA && CHAIN_OF_TRUST
 182         default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
 183         default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
 184         default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
 185         default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
 186         default 0x700000 if SYS_LS_PPA_FW_IN_MMC
 187         default 0x700000 if SYS_LS_PPA_FW_IN_NAND
 188         help
 189           If the PPA header firmware locate at XIP flash, such as NOR or
 190           QSPI flash, this address is a directly memory-mapped.
 191           If it is in a serial accessed flash, such as NAND and SD
 192           card, it is a byte offset.
 193
 194 config LS_PPA_ESBC_HDR_SIZE
 195         hex "Length of PPA ESBC header"
 196         depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
 197         default 0x2000
 198         help
 199           Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
 200           NAND to memory to validate PPA image.
 201
 202 endmenu
 203
 204 config SYS_FSL_ERRATUM_A010315
 205         bool "Workaround for PCIe erratum A010315"
 206
 207 config SYS_FSL_ERRATUM_A010539
 208         bool "Workaround for PIN MUX erratum A010539"
 209
 210 config MAX_CPUS
 211         int "Maximum number of CPUs permitted for Layerscape"
 212         default 4 if ARCH_LS1043A
 213         default 4 if ARCH_LS1046A
 214         default 16 if ARCH_LS2080A
 215         default 1
 216         help
 217           Set this number to the maximum number of possible CPUs in the SoC.
 218           SoCs may have multiple clusters with each cluster may have multiple
 219           ports. If some ports are reserved but higher ports are used for
 220           cores, count the reserved ports. This will allocate enough memory
 221           in spin table to properly handle all cores.
 222
 223 config SECURE_BOOT
 224         bool "Secure Boot"
 225         help
 226                 Enable Freescale Secure Boot feature
 227
 228 config QSPI_AHB_INIT
 229         bool "Init the QSPI AHB bus"
 230         help
 231           The default setting for QSPI AHB bus just support 3bytes addressing.
 232           But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
 233           bus for those flashes to support the full QSPI flash size.
 234
 235 config SYS_FSL_IFC_BANK_COUNT
 236         int "Maximum banks of Integrated flash controller"
 237         depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
 238         default 4 if ARCH_LS1043A
 239         default 4 if ARCH_LS1046A
 240         default 8 if ARCH_LS2080A
 241
 242 config SYS_FSL_HAS_DP_DDR
 243         bool
 244
 245 config SYS_FSL_SRDS_1
 246         bool
 247
 248 config SYS_FSL_SRDS_2
 249         bool
 250
 251 config SYS_HAS_SERDES
 252         bool
 253
 254 config FSL_TZASC_1
 255         bool
 256
 257 config FSL_TZASC_2
 258         bool
 259
 260 endmenu
 261
 262 menu "Layerscape clock tree configuration"
 263         depends on FSL_LSCH2 || FSL_LSCH3
 264
 265 config SYS_FSL_CLK
 266         bool "Enable clock tree initialization"
 267         default y
 268
 269 config CLUSTER_CLK_FREQ
 270         int "Reference clock of core cluster"
 271         depends on ARCH_LS1012A
 272         default 100000000
 273         help
 274           This number is the reference clock frequency of core PLL.
 275           For most platforms, the core PLL and Platform PLL have the same
 276           reference clock, but for some platforms, LS1012A for instance,
 277           they are provided sepatately.
 278
 279 config SYS_FSL_PCLK_DIV
 280         int "Platform clock divider"
 281         default 1 if ARCH_LS1043A
 282         default 1 if ARCH_LS1046A
 283         default 2
 284         help
 285           This is the divider that is used to derive Platform clock from
 286           Platform PLL, in another word:
 287                 Platform_clk = Platform_PLL_freq / this_divider
 288
 289 config SYS_FSL_DSPI_CLK_DIV
 290         int "DSPI clock divider"
 291         default 1 if ARCH_LS1043A
 292         default 2
 293         help
 294           This is the divider that is used to derive DSPI clock from Platform
 295           PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
 296
 297 config SYS_FSL_DUART_CLK_DIV
 298         int "DUART clock divider"
 299         default 1 if ARCH_LS1043A
 300         default 2
 301         help
 302           This is the divider that is used to derive DUART clock from Platform
 303           clock, in another word DUART_clk = Platform_clk / this_divider.
 304
 305 config SYS_FSL_I2C_CLK_DIV
 306         int "I2C clock divider"
 307         default 1 if ARCH_LS1043A
 308         default 2
 309         help
 310           This is the divider that is used to derive I2C clock from Platform
 311           clock, in another word I2C_clk = Platform_clk / this_divider.
 312
 313 config SYS_FSL_IFC_CLK_DIV
 314         int "IFC clock divider"
 315         default 1 if ARCH_LS1043A
 316         default 2
 317         help
 318           This is the divider that is used to derive IFC clock from Platform
 319           clock, in another word IFC_clk = Platform_clk / this_divider.
 320
 321 config SYS_FSL_LPUART_CLK_DIV
 322         int "LPUART clock divider"
 323         default 1 if ARCH_LS1043A
 324         default 2
 325         help
 326           This is the divider that is used to derive LPUART clock from Platform
 327           clock, in another word LPUART_clk = Platform_clk / this_divider.
 328
 329 config SYS_FSL_SDHC_CLK_DIV
 330         int "SDHC clock divider"
 331         default 1 if ARCH_LS1043A
 332         default 1 if ARCH_LS1012A
 333         default 2
 334         help
 335           This is the divider that is used to derive SDHC clock from Platform
 336           clock, in another word SDHC_clk = Platform_clk / this_divider.
 337 endmenu
 338
 339 config RESV_RAM
 340         bool
 341         help
 342           Reserve memory from the top, tracked by gd->arch.resv_ram. This
 343           reserved RAM can be used by special driver that resides in memory
 344           after U-Boot exits. It's up to implementation to allocate and allow
 345           access to this reserved memory. For example, the reserved RAM can
 346           be at the high end of physical memory. The reserve RAM may be
 347           excluded from memory bank(s) passed to OS, or marked as reserved.
 348
 349 config SYS_FSL_ERRATUM_A008336
 350         bool
 351
 352 config SYS_FSL_ERRATUM_A008514
 353         bool
 354
 355 config SYS_FSL_ERRATUM_A008585
 356         bool
 357
 358 config SYS_FSL_ERRATUM_A008850
 359         bool
 360
 361 config SYS_FSL_ERRATUM_A009203
 362         bool
 363
 364 config SYS_FSL_ERRATUM_A009635
 365         bool
 366
 367 config SYS_FSL_ERRATUM_A009660
 368         bool
 369
 370 config SYS_FSL_ERRATUM_A009929
 371         bool
 372
 373 config SYS_MC_RSV_MEM_ALIGN
 374         hex "Management Complex reserved memory alignment"
 375         depends on RESV_RAM
 376         default 0x20000000
 377         help
 378           Reserved memory needs to be aligned for MC to use. Default value
 379           is 512MB.