arch/arm/cpu/armv8/fsl-layerscape/Kconfig

   1 config ARCH_LS1012A
   2         bool
   3         select FSL_LSCH2
   4         select SYS_FSL_DDR_BE
   5         select SYS_FSL_MMDC
   6         select SYS_FSL_ERRATUM_A010315
   7
   8 config ARCH_LS1043A
   9         bool
  10         select FSL_LSCH2
  11         select SYS_FSL_DDR
  12         select SYS_FSL_DDR_BE
  13         select SYS_FSL_DDR_VER_50
  14         select SYS_FSL_ERRATUM_A008850
  15         select SYS_FSL_ERRATUM_A009660
  16         select SYS_FSL_ERRATUM_A009663
  17         select SYS_FSL_ERRATUM_A009929
  18         select SYS_FSL_ERRATUM_A009942
  19         select SYS_FSL_ERRATUM_A010315
  20         select SYS_FSL_ERRATUM_A010539
  21         select SYS_FSL_HAS_DDR3
  22         select SYS_FSL_HAS_DDR4
  23
  24 config ARCH_LS1046A
  25         bool
  26         select FSL_LSCH2
  27         select SYS_FSL_DDR
  28         select SYS_FSL_DDR_BE
  29         select SYS_FSL_DDR_VER_50
  30         select SYS_FSL_ERRATUM_A008511
  31         select SYS_FSL_ERRATUM_A009801
  32         select SYS_FSL_ERRATUM_A009803
  33         select SYS_FSL_ERRATUM_A009942
  34         select SYS_FSL_ERRATUM_A010165
  35         select SYS_FSL_ERRATUM_A010539
  36         select SYS_FSL_HAS_DDR4
  37         select SYS_FSL_SRDS_2
  38
  39 config ARCH_LS2080A
  40         bool
  41         select FSL_LSCH3
  42         select SYS_FSL_DDR
  43         select SYS_FSL_DDR_LE
  44         select SYS_FSL_DDR_VER_50
  45         select SYS_FSL_HAS_DP_DDR
  46         select SYS_FSL_HAS_SEC
  47         select SYS_FSL_HAS_DDR4
  48         select SYS_FSL_SEC_COMPAT_5
  49         select SYS_FSL_SEC_LE
  50         select SYS_FSL_SRDS_2
  51         select SYS_FSL_ERRATUM_A008336
  52         select SYS_FSL_ERRATUM_A008511
  53         select SYS_FSL_ERRATUM_A008514
  54         select SYS_FSL_ERRATUM_A008585
  55         select SYS_FSL_ERRATUM_A009635
  56         select SYS_FSL_ERRATUM_A009663
  57         select SYS_FSL_ERRATUM_A009801
  58         select SYS_FSL_ERRATUM_A009803
  59         select SYS_FSL_ERRATUM_A009942
  60         select SYS_FSL_ERRATUM_A010165
  61
  62 config FSL_LSCH2
  63         bool
  64         select SYS_FSL_HAS_SEC
  65         select SYS_FSL_SEC_COMPAT_5
  66         select SYS_FSL_SEC_BE
  67         select SYS_FSL_SRDS_1
  68         select SYS_HAS_SERDES
  69
  70 config FSL_LSCH3
  71         bool
  72         select SYS_FSL_SRDS_1
  73         select SYS_HAS_SERDES
  74
  75 menu "Layerscape architecture"
  76         depends on FSL_LSCH2 || FSL_LSCH3
  77
  78 menu "Layerscape PPA"
  79 config FSL_LS_PPA
  80         bool "FSL Layerscape PPA firmware support"
  81         depends on !ARMV8_PSCI
  82         depends on ARCH_LS1043A || ARCH_LS1046A
  83         select FSL_PPA_ARMV8_PSCI
  84         help
  85           The FSL Primary Protected Application (PPA) is a software component
  86           which is loaded during boot stage, and then remains resident in RAM
  87           and runs in the TrustZone after boot.
  88           Say y to enable it.
  89
  90 config FSL_PPA_ARMV8_PSCI
  91         bool "PSCI implementation in PPA firmware"
  92         depends on FSL_LS_PPA
  93         help
  94           This config enables the ARMv8 PSCI implementation in PPA firmware.
  95           This is a private PSCI implementation and different from those
  96           implemented under the common ARMv8 PSCI framework.
  97 endmenu
  98
  99 config SYS_FSL_ERRATUM_A010315
 100         bool "Workaround for PCIe erratum A010315"
 101
 102 config SYS_FSL_ERRATUM_A010539
 103         bool "Workaround for PIN MUX erratum A010539"
 104
 105 config MAX_CPUS
 106         int "Maximum number of CPUs permitted for Layerscape"
 107         default 4 if ARCH_LS1043A
 108         default 4 if ARCH_LS1046A
 109         default 16 if ARCH_LS2080A
 110         default 1
 111         help
 112           Set this number to the maximum number of possible CPUs in the SoC.
 113           SoCs may have multiple clusters with each cluster may have multiple
 114           ports. If some ports are reserved but higher ports are used for
 115           cores, count the reserved ports. This will allocate enough memory
 116           in spin table to properly handle all cores.
 117
 118 config NUM_DDR_CONTROLLERS
 119         int "Maximum DDR controllers"
 120         default 3 if ARCH_LS2080A
 121         default 1
 122
 123 config SECURE_BOOT
 124         bool
 125         help
 126                 Enable Freescale Secure Boot feature
 127
 128 config QSPI_AHB_INIT
 129         bool "Init the QSPI AHB bus"
 130         help
 131           The default setting for QSPI AHB bus just support 3bytes addressing.
 132           But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
 133           bus for those flashes to support the full QSPI flash size.
 134
 135 config SYS_FSL_IFC_BANK_COUNT
 136         int "Maximum banks of Integrated flash controller"
 137         depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
 138         default 4 if ARCH_LS1043A
 139         default 4 if ARCH_LS1046A
 140         default 8 if ARCH_LS2080A
 141
 142 config SYS_FSL_HAS_DP_DDR
 143         bool
 144
 145 config SYS_FSL_SRDS_1
 146         bool
 147
 148 config SYS_FSL_SRDS_2
 149         bool
 150
 151 config SYS_HAS_SERDES
 152         bool
 153
 154 endmenu
 155
 156 config SYS_FSL_ERRATUM_A008336
 157         bool
 158
 159 config SYS_FSL_ERRATUM_A008514
 160         bool
 161
 162 config SYS_FSL_ERRATUM_A008585
 163         bool
 164
 165 config SYS_FSL_ERRATUM_A008850
 166         bool
 167
 168 config SYS_FSL_ERRATUM_A009635
 169         bool
 170
 171 config SYS_FSL_ERRATUM_A009660
 172         bool
 173
 174 config SYS_FSL_ERRATUM_A009929
 175         bool