2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/errno.h>
10 #include <asm/system.h>
11 #include <asm/armv8/mmu.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/soc.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/speed.h>
18 #include <asm/arch/mp.h>
20 #include <efi_loader.h>
22 #include <fsl-mc/fsl_mc.h>
23 #ifdef CONFIG_FSL_ESDHC
24 #include <fsl_esdhc.h>
26 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
27 #include <asm/armv8/sec_firmware.h>
29 #ifdef CONFIG_SYS_FSL_DDR
33 DECLARE_GLOBAL_DATA_PTR
;
35 struct mm_region
*mem_map
= early_map
;
37 void cpu_name(char *name
)
39 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
40 unsigned int i
, svr
, ver
;
42 svr
= gur_in32(&gur
->svr
);
43 ver
= SVR_SOC_VER(svr
);
45 for (i
= 0; i
< ARRAY_SIZE(cpu_type_list
); i
++)
46 if ((cpu_type_list
[i
].soc_ver
& SVR_WO_E
) == ver
) {
47 strcpy(name
, cpu_type_list
[i
].name
);
49 if (IS_E_PROCESSOR(svr
))
52 sprintf(name
+ strlen(name
), " Rev%d.%d",
53 SVR_MAJ(svr
), SVR_MIN(svr
));
57 if (i
== ARRAY_SIZE(cpu_type_list
))
58 strcpy(name
, "unknown");
61 #ifndef CONFIG_SYS_DCACHE_OFF
63 * To start MMU before DDR is available, we create MMU table in SRAM.
64 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
65 * levels of translation tables here to cover 40-bit address space.
66 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
67 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
68 * Note, the debug print in cache_v8.c is not usable for debugging
69 * these early MMU tables because UART is not yet available.
71 static inline void early_mmu_setup(void)
73 unsigned int el
= current_el();
75 /* global data is already setup, no allocation yet */
76 gd
->arch
.tlb_addr
= CONFIG_SYS_FSL_OCRAM_BASE
;
77 gd
->arch
.tlb_fillptr
= gd
->arch
.tlb_addr
;
78 gd
->arch
.tlb_size
= EARLY_PGTABLE_SIZE
;
80 /* Create early page tables */
83 /* point TTBR to the new table */
84 set_ttbr_tcr_mair(el
, gd
->arch
.tlb_addr
,
85 get_tcr(el
, NULL
, NULL
) &
86 ~(TCR_ORGN_MASK
| TCR_IRGN_MASK
),
89 set_sctlr(get_sctlr() | CR_M
);
93 * The final tables look similar to early tables, but different in detail.
94 * These tables are in DRAM. Sub tables are added to enable cache for
97 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
98 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
100 static inline void final_mmu_setup(void)
102 u64 tlb_addr_save
= gd
->arch
.tlb_addr
;
103 unsigned int el
= current_el();
108 /* Update mapping for DDR to actual size */
109 for (index
= 0; index
< ARRAY_SIZE(final_map
) - 2; index
++) {
111 * Find the entry for DDR mapping and update the address and
112 * size. Zero-sized mapping will be skipped when creating MMU
115 switch (final_map
[index
].virt
) {
116 case CONFIG_SYS_FSL_DRAM_BASE1
:
117 final_map
[index
].virt
= gd
->bd
->bi_dram
[0].start
;
118 final_map
[index
].phys
= gd
->bd
->bi_dram
[0].start
;
119 final_map
[index
].size
= gd
->bd
->bi_dram
[0].size
;
121 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
122 case CONFIG_SYS_FSL_DRAM_BASE2
:
123 #if (CONFIG_NR_DRAM_BANKS >= 2)
124 final_map
[index
].virt
= gd
->bd
->bi_dram
[1].start
;
125 final_map
[index
].phys
= gd
->bd
->bi_dram
[1].start
;
126 final_map
[index
].size
= gd
->bd
->bi_dram
[1].size
;
128 final_map
[index
].size
= 0;
132 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
133 case CONFIG_SYS_FSL_DRAM_BASE3
:
134 #if (CONFIG_NR_DRAM_BANKS >= 3)
135 final_map
[index
].virt
= gd
->bd
->bi_dram
[2].start
;
136 final_map
[index
].phys
= gd
->bd
->bi_dram
[2].start
;
137 final_map
[index
].size
= gd
->bd
->bi_dram
[2].size
;
139 final_map
[index
].size
= 0;
148 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
149 if (gd
->arch
.secure_ram
& MEM_RESERVE_SECURE_MAINTAINED
) {
152 * Only use gd->arch.secure_ram if the address is
153 * recalculated. Align to 4KB for MMU table.
155 /* put page tables in secure ram */
156 index
= ARRAY_SIZE(final_map
) - 2;
157 gd
->arch
.tlb_addr
= gd
->arch
.secure_ram
& ~0xfff;
158 final_map
[index
].virt
= gd
->arch
.secure_ram
& ~0x3;
159 final_map
[index
].phys
= final_map
[index
].virt
;
160 final_map
[index
].size
= CONFIG_SYS_MEM_RESERVE_SECURE
;
161 final_map
[index
].attrs
= PTE_BLOCK_OUTER_SHARE
;
162 gd
->arch
.secure_ram
|= MEM_RESERVE_SECURE_SECURED
;
163 tlb_addr_save
= gd
->arch
.tlb_addr
;
165 /* Use allocated (board_f.c) memory for TLB */
166 tlb_addr_save
= gd
->arch
.tlb_allocated
;
167 gd
->arch
.tlb_addr
= tlb_addr_save
;
172 /* Reset the fill ptr */
173 gd
->arch
.tlb_fillptr
= tlb_addr_save
;
175 /* Create normal system page tables */
178 /* Create emergency page tables */
179 gd
->arch
.tlb_addr
= gd
->arch
.tlb_fillptr
;
180 gd
->arch
.tlb_emerg
= gd
->arch
.tlb_addr
;
182 gd
->arch
.tlb_addr
= tlb_addr_save
;
184 /* Disable cache and MMU */
185 dcache_disable(); /* TLBs are invalidated */
186 invalidate_icache_all();
188 /* point TTBR to the new table */
189 set_ttbr_tcr_mair(el
, gd
->arch
.tlb_addr
, get_tcr(el
, NULL
, NULL
),
192 set_sctlr(get_sctlr() | CR_M
);
195 u64
get_page_table_size(void)
200 int arch_cpu_init(void)
203 __asm_invalidate_dcache_all();
204 __asm_invalidate_tlb_all();
206 set_sctlr(get_sctlr() | CR_C
);
216 * This function is called from common/board_r.c.
217 * It recreates MMU table in main memory.
219 void enable_caches(void)
222 __asm_invalidate_tlb_all();
228 u32
initiator_type(u32 cluster
, int init_id
)
230 struct ccsr_gur
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
231 u32 idx
= (cluster
>> (init_id
* 8)) & TP_CLUSTER_INIT_MASK
;
234 type
= gur_in32(&gur
->tp_ityp
[idx
]);
235 if (type
& TP_ITYP_AV
)
241 u32
cpu_pos_mask(void)
243 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
245 u32 cluster
, type
, mask
= 0;
250 cluster
= gur_in32(&gur
->tp_cluster
[i
].lower
);
251 for (j
= 0; j
< TP_INIT_PER_CLUSTER
; j
++) {
252 type
= initiator_type(cluster
, j
);
253 if (type
&& (TP_ITYP_TYPE(type
) == TP_ITYP_TYPE_ARM
))
254 mask
|= 1 << (i
* TP_INIT_PER_CLUSTER
+ j
);
257 } while ((cluster
& TP_CLUSTER_EOC
) == 0x0);
264 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
265 int i
= 0, count
= 0;
266 u32 cluster
, type
, mask
= 0;
271 cluster
= gur_in32(&gur
->tp_cluster
[i
].lower
);
272 for (j
= 0; j
< TP_INIT_PER_CLUSTER
; j
++) {
273 type
= initiator_type(cluster
, j
);
275 if (TP_ITYP_TYPE(type
) == TP_ITYP_TYPE_ARM
)
281 } while ((cluster
& TP_CLUSTER_EOC
) == 0x0);
287 * Return the number of cores on this SOC.
289 int cpu_numcores(void)
291 return hweight32(cpu_mask());
294 int fsl_qoriq_core_to_cluster(unsigned int core
)
296 struct ccsr_gur __iomem
*gur
=
297 (void __iomem
*)(CONFIG_SYS_FSL_GUTS_ADDR
);
298 int i
= 0, count
= 0;
304 cluster
= gur_in32(&gur
->tp_cluster
[i
].lower
);
305 for (j
= 0; j
< TP_INIT_PER_CLUSTER
; j
++) {
306 if (initiator_type(cluster
, j
)) {
313 } while ((cluster
& TP_CLUSTER_EOC
) == 0x0);
315 return -1; /* cannot identify the cluster */
318 u32
fsl_qoriq_core_to_type(unsigned int core
)
320 struct ccsr_gur __iomem
*gur
=
321 (void __iomem
*)(CONFIG_SYS_FSL_GUTS_ADDR
);
322 int i
= 0, count
= 0;
328 cluster
= gur_in32(&gur
->tp_cluster
[i
].lower
);
329 for (j
= 0; j
< TP_INIT_PER_CLUSTER
; j
++) {
330 type
= initiator_type(cluster
, j
);
338 } while ((cluster
& TP_CLUSTER_EOC
) == 0x0);
340 return -1; /* cannot identify the cluster */
343 #ifndef CONFIG_FSL_LSCH3
346 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
348 return gur_in32(&gur
->svr
);
352 #ifdef CONFIG_DISPLAY_CPUINFO
353 int print_cpuinfo(void)
355 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
356 struct sys_info sysinfo
;
358 unsigned int i
, core
;
359 u32 type
, rcw
, svr
= gur_in32(&gur
->svr
);
364 printf(" %s (0x%x)\n", buf
, svr
);
365 memset((u8
*)buf
, 0x00, ARRAY_SIZE(buf
));
366 get_sys_info(&sysinfo
);
367 puts("Clock Configuration:");
368 for_each_cpu(i
, core
, cpu_numcores(), cpu_mask()) {
371 type
= TP_ITYP_VER(fsl_qoriq_core_to_type(core
));
372 printf("CPU%d(%s):%-4s MHz ", core
,
373 type
== TY_ITYP_VER_A7
? "A7 " :
374 (type
== TY_ITYP_VER_A53
? "A53" :
375 (type
== TY_ITYP_VER_A57
? "A57" :
376 (type
== TY_ITYP_VER_A72
? "A72" : " "))),
377 strmhz(buf
, sysinfo
.freq_processor
[core
]));
379 /* Display platform clock as Bus frequency. */
380 printf("\n Bus: %-4s MHz ",
381 strmhz(buf
, sysinfo
.freq_systembus
/ CONFIG_SYS_FSL_PCLK_DIV
));
382 printf("DDR: %-4s MT/s", strmhz(buf
, sysinfo
.freq_ddrbus
));
383 #ifdef CONFIG_SYS_DPAA_FMAN
384 printf(" FMAN: %-4s MHz", strmhz(buf
, sysinfo
.freq_fman
[0]));
386 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
387 if (soc_has_dp_ddr()) {
388 printf(" DP-DDR: %-4s MT/s",
389 strmhz(buf
, sysinfo
.freq_ddrbus2
));
395 * Display the RCW, so that no one gets confused as to what RCW
396 * we're actually using for this boot.
398 puts("Reset Configuration Word (RCW):");
399 for (i
= 0; i
< ARRAY_SIZE(gur
->rcwsr
); i
++) {
400 rcw
= gur_in32(&gur
->rcwsr
[i
]);
402 printf("\n %08x:", i
* 4);
403 printf(" %08x", rcw
);
411 #ifdef CONFIG_FSL_ESDHC
412 int cpu_mmc_init(bd_t
*bis
)
414 return fsl_esdhc_mmc_init(bis
);
418 int cpu_eth_init(bd_t
*bis
)
422 #ifdef CONFIG_FSL_MC_ENET
423 error
= fsl_mc_ldpaa_init(bis
);
425 #ifdef CONFIG_FMAN_ENET
426 fm_standard_init(bis
);
431 int arch_early_init_r(void)
435 u32 psci_ver
= 0xffffffff;
438 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
441 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
442 erratum_a009942_check_cpo();
445 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
446 defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
447 /* Check the psci version to determine if the psci is supported */
448 psci_ver
= sec_firmware_support_psci_version();
450 if (psci_ver
== 0xffffffff) {
451 rv
= fsl_layerscape_wake_seconday_cores();
453 printf("Did not wake secondary cores\n");
457 #ifdef CONFIG_SYS_HAS_SERDES
460 #ifdef CONFIG_FMAN_ENET
468 u32 __iomem
*cntcr
= (u32
*)CONFIG_SYS_FSL_TIMER_ADDR
;
469 #ifdef CONFIG_FSL_LSCH3
470 u32 __iomem
*cltbenr
= (u32
*)CONFIG_SYS_FSL_PMU_CLTBENR
;
472 #ifdef CONFIG_LS2080A
473 u32 __iomem
*pctbenr
= (u32
*)FSL_PMU_PCTBENR_OFFSET
;
476 #ifdef COUNTER_FREQUENCY_REAL
477 unsigned long cntfrq
= COUNTER_FREQUENCY_REAL
;
479 /* Update with accurate clock frequency */
480 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq
) : "memory");
483 #ifdef CONFIG_FSL_LSCH3
484 /* Enable timebase for all clusters.
485 * It is safe to do so even some clusters are not enabled.
487 out_le32(cltbenr
, 0xf);
490 #ifdef CONFIG_LS2080A
492 * In certain Layerscape SoCs, the clock for each core's
493 * has an enable bit in the PMU Physical Core Time Base Enable
494 * Register (PCTBENR), which allows the watchdog to operate.
496 setbits_le32(pctbenr
, 0xff);
498 * For LS2080A SoC and its personalities, timer controller
499 * offset is different
501 svr_dev_id
= get_svr() >> 16;
502 if (svr_dev_id
== SVR_DEV_LS2080A
)
503 cntcr
= (u32
*)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR
;
507 /* Enable clock for timer
508 * This is a global setting.
510 out_le32(cntcr
, 0x1);
515 __efi_runtime_data u32 __iomem
*rstcr
= (u32
*)CONFIG_SYS_FSL_RST_ADDR
;
517 void __efi_runtime
reset_cpu(ulong addr
)
521 /* Raise RESET_REQ_B */
522 val
= scfg_in32(rstcr
);
524 scfg_out32(rstcr
, val
);
527 #ifdef CONFIG_EFI_LOADER
529 void __efi_runtime EFIAPI
efi_reset_system(
530 enum efi_reset_type reset_type
,
531 efi_status_t reset_status
,
532 unsigned long data_size
, void *reset_data
)
534 switch (reset_type
) {
539 case EFI_RESET_SHUTDOWN
:
540 /* Nothing we can do */
547 void efi_reset_system_init(void)
549 efi_add_runtime_mmio(&rstcr
, sizeof(*rstcr
));
554 phys_size_t
board_reserve_ram_top(phys_size_t ram_size
)
556 phys_size_t ram_top
= ram_size
;
558 #ifdef CONFIG_FSL_MC_ENET
559 /* The start address of MC reserved memory needs to be aligned. */
560 ram_top
-= mc_get_dram_block_size();
561 ram_top
&= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN
- 1);
564 return ram_size
- ram_top
;
567 phys_size_t
get_effective_memsize(void)
569 phys_size_t ea_size
, rem
= 0;
572 * For ARMv8 SoCs, DDR memory is split into two or three regions. The
573 * first region is 2GB space at 0x8000_0000. If the memory extends to
574 * the second region (or the third region if applicable), the secure
575 * memory and Management Complex (MC) memory should be put into the
576 * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED
577 * is set to the size of first region so U-Boot doesn't relocate itself
578 * into higher address. Should DDR be configured to skip the first
579 * region, this function needs to be adjusted.
581 if (gd
->ram_size
> CONFIG_MAX_MEM_MAPPED
) {
582 ea_size
= CONFIG_MAX_MEM_MAPPED
;
583 rem
= gd
->ram_size
- ea_size
;
585 ea_size
= gd
->ram_size
;
588 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
589 /* Check if we have enough space for secure memory */
590 if (rem
> CONFIG_SYS_MEM_RESERVE_SECURE
) {
591 rem
-= CONFIG_SYS_MEM_RESERVE_SECURE
;
593 if (ea_size
> CONFIG_SYS_MEM_RESERVE_SECURE
) {
594 ea_size
-= CONFIG_SYS_MEM_RESERVE_SECURE
;
595 rem
= 0; /* Presume MC requires more memory */
597 printf("Error: No enough space for secure memory.\n");
601 /* Check if we have enough memory for MC */
602 if (rem
< board_reserve_ram_top(rem
)) {
603 /* Not enough memory in high region to reserve */
604 if (ea_size
> board_reserve_ram_top(rem
))
605 ea_size
-= board_reserve_ram_top(rem
);
607 printf("Error: No enough space for reserved memory.\n");
613 void dram_init_banksize(void)
615 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
616 phys_size_t dp_ddr_size
;
620 * gd->ram_size has the total size of DDR memory, less reserved secure
621 * memory. The DDR extends from low region to high region(s) presuming
622 * no hole is created with DDR configuration. gd->arch.secure_ram tracks
623 * the location of secure memory. gd->arch.resv_ram tracks the location
624 * of reserved memory for Management Complex (MC).
626 gd
->bd
->bi_dram
[0].start
= CONFIG_SYS_SDRAM_BASE
;
627 if (gd
->ram_size
> CONFIG_SYS_DDR_BLOCK1_SIZE
) {
628 gd
->bd
->bi_dram
[0].size
= CONFIG_SYS_DDR_BLOCK1_SIZE
;
629 gd
->bd
->bi_dram
[1].start
= CONFIG_SYS_DDR_BLOCK2_BASE
;
630 gd
->bd
->bi_dram
[1].size
= gd
->ram_size
-
631 CONFIG_SYS_DDR_BLOCK1_SIZE
;
632 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
633 if (gd
->bi_dram
[1].size
> CONFIG_SYS_DDR_BLOCK2_SIZE
) {
634 gd
->bd
->bi_dram
[2].start
= CONFIG_SYS_DDR_BLOCK3_BASE
;
635 gd
->bd
->bi_dram
[2].size
= gd
->bd
->bi_dram
[1].size
-
636 CONFIG_SYS_DDR_BLOCK2_SIZE
;
637 gd
->bd
->bi_dram
[1].size
= CONFIG_SYS_DDR_BLOCK2_SIZE
;
641 gd
->bd
->bi_dram
[0].size
= gd
->ram_size
;
643 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
644 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
645 if (gd
->bd
->bi_dram
[2].size
>= CONFIG_SYS_MEM_RESERVE_SECURE
) {
646 gd
->bd
->bi_dram
[2].size
-= CONFIG_SYS_MEM_RESERVE_SECURE
;
647 gd
->arch
.secure_ram
= gd
->bd
->bi_dram
[2].start
+
648 gd
->bd
->bi_dram
[2].size
;
649 gd
->arch
.secure_ram
|= MEM_RESERVE_SECURE_MAINTAINED
;
650 gd
->ram_size
-= CONFIG_SYS_MEM_RESERVE_SECURE
;
654 if (gd
->bd
->bi_dram
[1].size
>= CONFIG_SYS_MEM_RESERVE_SECURE
) {
655 gd
->bd
->bi_dram
[1].size
-=
656 CONFIG_SYS_MEM_RESERVE_SECURE
;
657 gd
->arch
.secure_ram
= gd
->bd
->bi_dram
[1].start
+
658 gd
->bd
->bi_dram
[1].size
;
659 gd
->arch
.secure_ram
|= MEM_RESERVE_SECURE_MAINTAINED
;
660 gd
->ram_size
-= CONFIG_SYS_MEM_RESERVE_SECURE
;
661 } else if (gd
->bd
->bi_dram
[0].size
>
662 CONFIG_SYS_MEM_RESERVE_SECURE
) {
663 gd
->bd
->bi_dram
[0].size
-=
664 CONFIG_SYS_MEM_RESERVE_SECURE
;
665 gd
->arch
.secure_ram
= gd
->bd
->bi_dram
[0].start
+
666 gd
->bd
->bi_dram
[0].size
;
667 gd
->arch
.secure_ram
|= MEM_RESERVE_SECURE_MAINTAINED
;
668 gd
->ram_size
-= CONFIG_SYS_MEM_RESERVE_SECURE
;
671 #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
673 #ifdef CONFIG_FSL_MC_ENET
674 /* Assign memory for MC */
675 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
676 if (gd
->bd
->bi_dram
[2].size
>=
677 board_reserve_ram_top(gd
->bd
->bi_dram
[2].size
)) {
678 gd
->arch
.resv_ram
= gd
->bd
->bi_dram
[2].start
+
679 gd
->bd
->bi_dram
[2].size
-
680 board_reserve_ram_top(gd
->bd
->bi_dram
[2].size
);
684 if (gd
->bd
->bi_dram
[1].size
>=
685 board_reserve_ram_top(gd
->bd
->bi_dram
[1].size
)) {
686 gd
->arch
.resv_ram
= gd
->bd
->bi_dram
[1].start
+
687 gd
->bd
->bi_dram
[1].size
-
688 board_reserve_ram_top(gd
->bd
->bi_dram
[1].size
);
689 } else if (gd
->bd
->bi_dram
[0].size
>
690 board_reserve_ram_top(gd
->bd
->bi_dram
[0].size
)) {
691 gd
->arch
.resv_ram
= gd
->bd
->bi_dram
[0].start
+
692 gd
->bd
->bi_dram
[0].size
-
693 board_reserve_ram_top(gd
->bd
->bi_dram
[0].size
);
696 #endif /* CONFIG_FSL_MC_ENET */
698 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
699 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
700 #error "This SoC shouldn't have DP DDR"
702 if (soc_has_dp_ddr()) {
703 /* initialize DP-DDR here */
706 * DDR controller use 0 as the base address for binding.
707 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
709 dp_ddr_size
= fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY
,
711 CONFIG_DP_DDR_NUM_CTRLS
,
712 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
,
715 gd
->bd
->bi_dram
[2].start
= CONFIG_SYS_DP_DDR_BASE
;
716 gd
->bd
->bi_dram
[2].size
= dp_ddr_size
;
718 puts("Not detected");
724 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
725 void efi_add_known_memory(void)
728 phys_addr_t ram_start
, start
;
729 phys_size_t ram_size
;
733 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++) {
734 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
735 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
736 #error "This SoC shouldn't have DP DDR"
739 continue; /* skip DP-DDR */
741 ram_start
= gd
->bd
->bi_dram
[i
].start
;
742 ram_size
= gd
->bd
->bi_dram
[i
].size
;
743 #ifdef CONFIG_RESV_RAM
744 if (gd
->arch
.resv_ram
>= ram_start
&&
745 gd
->arch
.resv_ram
< ram_start
+ ram_size
)
746 ram_size
= gd
->arch
.resv_ram
- ram_start
;
748 start
= (ram_start
+ EFI_PAGE_MASK
) & ~EFI_PAGE_MASK
;
749 pages
= (ram_size
+ EFI_PAGE_MASK
) >> EFI_PAGE_SHIFT
;
751 efi_add_memory_map(start
, pages
, EFI_CONVENTIONAL_MEMORY
,
758 * Before DDR size is known, early MMU table have DDR mapped as device memory
759 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
760 * needs to be set for these mappings.
761 * If a special case configures DDR with holes in the mapping, the holes need
762 * to be marked as invalid. This is not implemented in this function.
764 void update_early_mmu_table(void)
766 if (!gd
->arch
.tlb_addr
)
769 if (gd
->ram_size
<= CONFIG_SYS_FSL_DRAM_SIZE1
) {
770 mmu_change_region_attr(
771 CONFIG_SYS_SDRAM_BASE
,
773 PTE_BLOCK_MEMTYPE(MT_NORMAL
) |
774 PTE_BLOCK_OUTER_SHARE
|
778 mmu_change_region_attr(
779 CONFIG_SYS_SDRAM_BASE
,
780 CONFIG_SYS_DDR_BLOCK1_SIZE
,
781 PTE_BLOCK_MEMTYPE(MT_NORMAL
) |
782 PTE_BLOCK_OUTER_SHARE
|
785 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
786 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
787 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
789 if (gd
->ram_size
- CONFIG_SYS_DDR_BLOCK1_SIZE
>
790 CONFIG_SYS_DDR_BLOCK2_SIZE
) {
791 mmu_change_region_attr(
792 CONFIG_SYS_DDR_BLOCK2_BASE
,
793 CONFIG_SYS_DDR_BLOCK2_SIZE
,
794 PTE_BLOCK_MEMTYPE(MT_NORMAL
) |
795 PTE_BLOCK_OUTER_SHARE
|
798 mmu_change_region_attr(
799 CONFIG_SYS_DDR_BLOCK3_BASE
,
801 CONFIG_SYS_DDR_BLOCK1_SIZE
-
802 CONFIG_SYS_DDR_BLOCK2_SIZE
,
803 PTE_BLOCK_MEMTYPE(MT_NORMAL
) |
804 PTE_BLOCK_OUTER_SHARE
|
810 mmu_change_region_attr(
811 CONFIG_SYS_DDR_BLOCK2_BASE
,
813 CONFIG_SYS_DDR_BLOCK1_SIZE
,
814 PTE_BLOCK_MEMTYPE(MT_NORMAL
) |
815 PTE_BLOCK_OUTER_SHARE
|
822 __weak
int dram_init(void)
824 gd
->ram_size
= initdram(0);
825 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
826 /* This will break-before-make MMU for DDR */
827 update_early_mmu_table();