arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 /*
   2  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/errno.h>
  10 #include <asm/system.h>
  11 #include <asm/armv8/mmu.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/soc.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/speed.h>
  17 #ifdef CONFIG_MP
  18 #include <asm/arch/mp.h>
  19 #endif
  20 #include <fm_eth.h>
  21 #include <fsl_debug_server.h>
  22 #include <fsl-mc/fsl_mc.h>
  23 #ifdef CONFIG_FSL_ESDHC
  24 #include <fsl_esdhc.h>
  25 #endif
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 void cpu_name(char *name)
  30 {
  31         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  32         unsigned int i, svr, ver;
  33
  34         svr = gur_in32(&gur->svr);
  35         ver = SVR_SOC_VER(svr);
  36
  37         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
  38                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
  39                         strcpy(name, cpu_type_list[i].name);
  40
  41                         if (IS_E_PROCESSOR(svr))
  42                                 strcat(name, "E");
  43                         break;
  44                 }
  45
  46         if (i == ARRAY_SIZE(cpu_type_list))
  47                 strcpy(name, "unknown");
  48 }
  49
  50 #ifndef CONFIG_SYS_DCACHE_OFF
  51 /*
  52  * Set the block entries according to the information of the table.
  53  */
  54 static int set_block_entry(const struct sys_mmu_table *list,
  55                            struct table_info *table)
  56 {
  57         u64 block_size = 0, block_shift = 0;
  58         u64 block_addr, index;
  59         int j;
  60
  61         if (table->entry_size == BLOCK_SIZE_L1) {
  62                 block_size = BLOCK_SIZE_L1;
  63                 block_shift = SECTION_SHIFT_L1;
  64         } else if (table->entry_size == BLOCK_SIZE_L2) {
  65                 block_size = BLOCK_SIZE_L2;
  66                 block_shift = SECTION_SHIFT_L2;
  67         } else {
  68                 return -EINVAL;
  69         }
  70
  71         block_addr = list->phys_addr;
  72         index = (list->virt_addr - table->table_base) >> block_shift;
  73
  74         for (j = 0; j < (list->size >> block_shift); j++) {
  75                 set_pgtable_section(table->ptr,
  76                                     index,
  77                                     block_addr,
  78                                     list->memory_type,
  79                                     list->share);
  80                 block_addr += block_size;
  81                 index++;
  82         }
  83
  84         return 0;
  85 }
  86
  87 /*
  88  * Find the corresponding table entry for the list.
  89  */
  90 static int find_table(const struct sys_mmu_table *list,
  91                       struct table_info *table, u64 *level0_table)
  92 {
  93         u64 index = 0, level = 0;
  94         u64 *level_table = level0_table;
  95         u64 temp_base = 0, block_size = 0, block_shift = 0;
  96
  97         while (level < 3) {
  98                 if (level == 0) {
  99                         block_size = BLOCK_SIZE_L0;
 100                         block_shift = SECTION_SHIFT_L0;
 101                 } else if (level == 1) {
 102                         block_size = BLOCK_SIZE_L1;
 103                         block_shift = SECTION_SHIFT_L1;
 104                 } else if (level == 2) {
 105                         block_size = BLOCK_SIZE_L2;
 106                         block_shift = SECTION_SHIFT_L2;
 107                 }
 108
 109                 index = 0;
 110                 while (list->virt_addr >= temp_base) {
 111                         index++;
 112                         temp_base += block_size;
 113                 }
 114
 115                 temp_base -= block_size;
 116
 117                 if ((level_table[index - 1] & PMD_TYPE_MASK) ==
 118                     PMD_TYPE_TABLE) {
 119                         level_table = (u64 *)(level_table[index - 1] &
 120                                       ~PMD_TYPE_MASK);
 121                         level++;
 122                         continue;
 123                 } else {
 124                         if (level == 0)
 125                                 return -EINVAL;
 126
 127                         if ((list->phys_addr + list->size) >
 128                             (temp_base + block_size * NUM_OF_ENTRY))
 129                                 return -EINVAL;
 130
 131                         /*
 132                          * Check the address and size of the list member is
 133                          * aligned with the block size.
 134                          */
 135                         if (((list->phys_addr & (block_size - 1)) != 0) ||
 136                             ((list->size & (block_size - 1)) != 0))
 137                                 return -EINVAL;
 138
 139                         table->ptr = level_table;
 140                         table->table_base = temp_base -
 141                                             ((index - 1) << block_shift);
 142                         table->entry_size = block_size;
 143
 144                         return 0;
 145                 }
 146         }
 147         return -EINVAL;
 148 }
 149
 150 /*
 151  * To start MMU before DDR is available, we create MMU table in SRAM.
 152  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
 153  * levels of translation tables here to cover 40-bit address space.
 154  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
 155  * Level 0 IA[39], table address @0
 156  * Level 1 IA[38:30], table address @0x1000, 0x2000
 157  * Level 2 IA[29:21], table address @0x3000, 0x4000
 158  * Address above 0x5000 is free for other purpose.
 159  */
 160 static inline void early_mmu_setup(void)
 161 {
 162         unsigned int el, i;
 163         u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE;
 164         u64 *level1_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000);
 165         u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
 166         u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
 167         u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000);
 168
 169         struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
 170
 171         /* Invalidate all table entries */
 172         memset(level0_table, 0, 0x5000);
 173
 174         /* Fill in the table entries */
 175         set_pgtable_table(level0_table, 0, level1_table0);
 176         set_pgtable_table(level0_table, 1, level1_table1);
 177         set_pgtable_table(level1_table0, 0, level2_table0);
 178
 179 #ifdef CONFIG_FSL_LSCH3
 180         set_pgtable_table(level1_table0,
 181                           CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1,
 182                           level2_table1);
 183 #endif
 184         /* Find the table and fill in the block entries */
 185         for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) {
 186                 if (find_table(&early_mmu_table[i],
 187                                &table, level0_table) == 0) {
 188                         /*
 189                          * If find_table() returns error, it cannot be dealt
 190                          * with here. Breakpoint can be added for debugging.
 191                          */
 192                         set_block_entry(&early_mmu_table[i], &table);
 193                         /*
 194                          * If set_block_entry() returns error, it cannot be
 195                          * dealt with here too.
 196                          */
 197                 }
 198         }
 199
 200         el = current_el();
 201
 202         set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR,
 203                           MEMORY_ATTRIBUTES);
 204         set_sctlr(get_sctlr() | CR_M);
 205 }
 206
 207 /*
 208  * The final tables look similar to early tables, but different in detail.
 209  * These tables are in DRAM. Sub tables are added to enable cache for
 210  * QBMan and OCRAM.
 211  *
 212  * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB.
 213  * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB.
 214  * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB.
 215  *
 216  * For LSCH3:
 217  * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB.
 218  */
 219 static inline void final_mmu_setup(void)
 220 {
 221         unsigned int el, i;
 222         u64 *level0_table = (u64 *)gd->arch.tlb_addr;
 223         u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000);
 224         u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000);
 225         u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
 226 #ifdef CONFIG_FSL_LSCH3
 227         u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
 228 #endif
 229         struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
 230
 231         /* Invalidate all table entries */
 232         memset(level0_table, 0, PGTABLE_SIZE);
 233
 234         /* Fill in the table entries */
 235         set_pgtable_table(level0_table, 0, level1_table0);
 236         set_pgtable_table(level0_table, 1, level1_table1);
 237         set_pgtable_table(level1_table0, 0, level2_table0);
 238 #ifdef CONFIG_FSL_LSCH3
 239         set_pgtable_table(level1_table0,
 240                           CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
 241                           level2_table1);
 242 #endif
 243
 244         /* Find the table and fill in the block entries */
 245         for (i = 0; i < ARRAY_SIZE(final_mmu_table); i++) {
 246                 if (find_table(&final_mmu_table[i],
 247                                &table, level0_table) == 0) {
 248                         if (set_block_entry(&final_mmu_table[i],
 249                                             &table) != 0) {
 250                                 printf("MMU error: could not set block entry for %p\n",
 251                                        &final_mmu_table[i]);
 252                         }
 253
 254                 } else {
 255                         printf("MMU error: could not find the table for %p\n",
 256                                &final_mmu_table[i]);
 257                 }
 258         }
 259
 260         /* flush new MMU table */
 261         flush_dcache_range(gd->arch.tlb_addr,
 262                            gd->arch.tlb_addr + gd->arch.tlb_size);
 263
 264         /* point TTBR to the new table */
 265         el = current_el();
 266
 267         set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
 268                           MEMORY_ATTRIBUTES);
 269         /*
 270          * MMU is already enabled, just need to invalidate TLB to load the
 271          * new table. The new table is compatible with the current table, if
 272          * MMU somehow walks through the new table before invalidation TLB,
 273          * it still works. So we don't need to turn off MMU here.
 274          */
 275 }
 276
 277 int arch_cpu_init(void)
 278 {
 279         icache_enable();
 280         __asm_invalidate_dcache_all();
 281         __asm_invalidate_tlb_all();
 282         early_mmu_setup();
 283         set_sctlr(get_sctlr() | CR_C);
 284         return 0;
 285 }
 286
 287 /*
 288  * This function is called from lib/board.c.
 289  * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
 290  * There is no need to disable d-cache for this operation.
 291  */
 292 void enable_caches(void)
 293 {
 294         final_mmu_setup();
 295         __asm_invalidate_tlb_all();
 296 }
 297 #endif
 298
 299 static inline u32 initiator_type(u32 cluster, int init_id)
 300 {
 301         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 302         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 303         u32 type = 0;
 304
 305         type = gur_in32(&gur->tp_ityp[idx]);
 306         if (type & TP_ITYP_AV)
 307                 return type;
 308
 309         return 0;
 310 }
 311
 312 u32 cpu_mask(void)
 313 {
 314         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 315         int i = 0, count = 0;
 316         u32 cluster, type, mask = 0;
 317
 318         do {
 319                 int j;
 320
 321                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 322                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 323                         type = initiator_type(cluster, j);
 324                         if (type) {
 325                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 326                                         mask |= 1 << count;
 327                                 count++;
 328                         }
 329                 }
 330                 i++;
 331         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 332
 333         return mask;
 334 }
 335
 336 /*
 337  * Return the number of cores on this SOC.
 338  */
 339 int cpu_numcores(void)
 340 {
 341         return hweight32(cpu_mask());
 342 }
 343
 344 int fsl_qoriq_core_to_cluster(unsigned int core)
 345 {
 346         struct ccsr_gur __iomem *gur =
 347                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 348         int i = 0, count = 0;
 349         u32 cluster;
 350
 351         do {
 352                 int j;
 353
 354                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 355                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 356                         if (initiator_type(cluster, j)) {
 357                                 if (count == core)
 358                                         return i;
 359                                 count++;
 360                         }
 361                 }
 362                 i++;
 363         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 364
 365         return -1;      /* cannot identify the cluster */
 366 }
 367
 368 u32 fsl_qoriq_core_to_type(unsigned int core)
 369 {
 370         struct ccsr_gur __iomem *gur =
 371                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 372         int i = 0, count = 0;
 373         u32 cluster, type;
 374
 375         do {
 376                 int j;
 377
 378                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 379                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 380                         type = initiator_type(cluster, j);
 381                         if (type) {
 382                                 if (count == core)
 383                                         return type;
 384                                 count++;
 385                         }
 386                 }
 387                 i++;
 388         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 389
 390         return -1;      /* cannot identify the cluster */
 391 }
 392
 393 #ifdef CONFIG_DISPLAY_CPUINFO
 394 int print_cpuinfo(void)
 395 {
 396         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 397         struct sys_info sysinfo;
 398         char buf[32];
 399         unsigned int i, core;
 400         u32 type, rcw;
 401
 402         puts("SoC: ");
 403
 404         cpu_name(buf);
 405         printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr));
 406         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 407         get_sys_info(&sysinfo);
 408         puts("Clock Configuration:");
 409         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
 410                 if (!(i % 3))
 411                         puts("\n       ");
 412                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
 413                 printf("CPU%d(%s):%-4s MHz  ", core,
 414                        type == TY_ITYP_VER_A7 ? "A7 " :
 415                        (type == TY_ITYP_VER_A53 ? "A53" :
 416                         (type == TY_ITYP_VER_A57 ? "A57" : "   ")),
 417                        strmhz(buf, sysinfo.freq_processor[core]));
 418         }
 419         printf("\n       Bus:      %-4s MHz  ",
 420                strmhz(buf, sysinfo.freq_systembus));
 421         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
 422 #ifdef CONFIG_FSL_LSCH3
 423         printf("     DP-DDR:   %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
 424 #endif
 425         puts("\n");
 426
 427         /*
 428          * Display the RCW, so that no one gets confused as to what RCW
 429          * we're actually using for this boot.
 430          */
 431         puts("Reset Configuration Word (RCW):");
 432         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
 433                 rcw = gur_in32(&gur->rcwsr[i]);
 434                 if ((i % 4) == 0)
 435                         printf("\n       %08x:", i * 4);
 436                 printf(" %08x", rcw);
 437         }
 438         puts("\n");
 439
 440         return 0;
 441 }
 442 #endif
 443
 444 #ifdef CONFIG_FSL_ESDHC
 445 int cpu_mmc_init(bd_t *bis)
 446 {
 447         return fsl_esdhc_mmc_init(bis);
 448 }
 449 #endif
 450
 451 int cpu_eth_init(bd_t *bis)
 452 {
 453         int error = 0;
 454
 455 #ifdef CONFIG_FSL_MC_ENET
 456         error = fsl_mc_ldpaa_init(bis);
 457 #endif
 458         return error;
 459 }
 460
 461 int arch_early_init_r(void)
 462 {
 463 #ifdef CONFIG_MP
 464         int rv = 1;
 465
 466         rv = fsl_layerscape_wake_seconday_cores();
 467         if (rv)
 468                 printf("Did not wake secondary cores\n");
 469 #endif
 470
 471 #ifdef CONFIG_SYS_HAS_SERDES
 472         fsl_serdes_init();
 473 #endif
 474         return 0;
 475 }
 476
 477 int timer_init(void)
 478 {
 479         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 480 #ifdef CONFIG_FSL_LSCH3
 481         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 482 #endif
 483 #ifdef COUNTER_FREQUENCY_REAL
 484         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 485
 486         /* Update with accurate clock frequency */
 487         asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
 488 #endif
 489
 490 #ifdef CONFIG_FSL_LSCH3
 491         /* Enable timebase for all clusters.
 492          * It is safe to do so even some clusters are not enabled.
 493          */
 494         out_le32(cltbenr, 0xf);
 495 #endif
 496
 497         /* Enable clock for timer
 498          * This is a global setting.
 499          */
 500         out_le32(cntcr, 0x1);
 501
 502         return 0;
 503 }
 504
 505 void reset_cpu(ulong addr)
 506 {
 507         u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
 508         u32 val;
 509
 510         /* Raise RESET_REQ_B */
 511         val = scfg_in32(rstcr);
 512         val |= 0x02;
 513         scfg_out32(rstcr, val);
 514 }