arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 /*
   2  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/errno.h>
  10 #include <asm/system.h>
  11 #include <asm/armv8/mmu.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/soc.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/speed.h>
  17 #ifdef CONFIG_MP
  18 #include <asm/arch/mp.h>
  19 #endif
  20 #include <fm_eth.h>
  21 #include <fsl_debug_server.h>
  22 #include <fsl-mc/fsl_mc.h>
  23 #ifdef CONFIG_FSL_ESDHC
  24 #include <fsl_esdhc.h>
  25 #endif
  26 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
  27 #include <asm/armv8/sec_firmware.h>
  28 #endif
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 struct mm_region *mem_map = early_map;
  33
  34 void cpu_name(char *name)
  35 {
  36         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  37         unsigned int i, svr, ver;
  38
  39         svr = gur_in32(&gur->svr);
  40         ver = SVR_SOC_VER(svr);
  41
  42         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
  43                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
  44                         strcpy(name, cpu_type_list[i].name);
  45
  46                         if (IS_E_PROCESSOR(svr))
  47                                 strcat(name, "E");
  48                         break;
  49                 }
  50
  51         if (i == ARRAY_SIZE(cpu_type_list))
  52                 strcpy(name, "unknown");
  53 }
  54
  55 #ifndef CONFIG_SYS_DCACHE_OFF
  56 /*
  57  * To start MMU before DDR is available, we create MMU table in SRAM.
  58  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
  59  * levels of translation tables here to cover 40-bit address space.
  60  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
  61  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
  62  * Note, the debug print in cache_v8.c is not usable for debugging
  63  * these early MMU tables because UART is not yet available.
  64  */
  65 static inline void early_mmu_setup(void)
  66 {
  67         unsigned int el = current_el();
  68
  69         /* global data is already setup, no allocation yet */
  70         gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
  71         gd->arch.tlb_fillptr = gd->arch.tlb_addr;
  72         gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
  73
  74         /* Create early page tables */
  75         setup_pgtables();
  76
  77         /* point TTBR to the new table */
  78         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
  79                           get_tcr(el, NULL, NULL) &
  80                           ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
  81                           MEMORY_ATTRIBUTES);
  82
  83         set_sctlr(get_sctlr() | CR_M);
  84 }
  85
  86 /*
  87  * The final tables look similar to early tables, but different in detail.
  88  * These tables are in DRAM. Sub tables are added to enable cache for
  89  * QBMan and OCRAM.
  90  *
  91  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
  92  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
  93  */
  94 static inline void final_mmu_setup(void)
  95 {
  96         u64 tlb_addr_save = gd->arch.tlb_addr;
  97         unsigned int el = current_el();
  98 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  99         int index;
 100 #endif
 101
 102         mem_map = final_map;
 103
 104 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 105         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 106                 if (el == 3) {
 107                         /*
 108                          * Only use gd->arch.secure_ram if the address is
 109                          * recalculated. Align to 4KB for MMU table.
 110                          */
 111                         /* put page tables in secure ram */
 112                         index = ARRAY_SIZE(final_map) - 2;
 113                         gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 114                         final_map[index].virt = gd->arch.secure_ram & ~0x3;
 115                         final_map[index].phys = final_map[index].virt;
 116                         final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 117                         final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 118                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 119                         tlb_addr_save = gd->arch.tlb_addr;
 120                 } else {
 121                         /* Use allocated (board_f.c) memory for TLB */
 122                         tlb_addr_save = gd->arch.tlb_allocated;
 123                         gd->arch.tlb_addr = tlb_addr_save;
 124                 }
 125         }
 126 #endif
 127
 128         /* Reset the fill ptr */
 129         gd->arch.tlb_fillptr = tlb_addr_save;
 130
 131         /* Create normal system page tables */
 132         setup_pgtables();
 133
 134         /* Create emergency page tables */
 135         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 136         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 137         setup_pgtables();
 138         gd->arch.tlb_addr = tlb_addr_save;
 139
 140         /* flush new MMU table */
 141         flush_dcache_range(gd->arch.tlb_addr,
 142                            gd->arch.tlb_addr + gd->arch.tlb_size);
 143
 144         /* point TTBR to the new table */
 145         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 146                           MEMORY_ATTRIBUTES);
 147         /*
 148          * MMU is already enabled, just need to invalidate TLB to load the
 149          * new table. The new table is compatible with the current table, if
 150          * MMU somehow walks through the new table before invalidation TLB,
 151          * it still works. So we don't need to turn off MMU here.
 152          */
 153 }
 154
 155 u64 get_page_table_size(void)
 156 {
 157         return 0x10000;
 158 }
 159
 160 int arch_cpu_init(void)
 161 {
 162         icache_enable();
 163         __asm_invalidate_dcache_all();
 164         __asm_invalidate_tlb_all();
 165         early_mmu_setup();
 166         set_sctlr(get_sctlr() | CR_C);
 167         return 0;
 168 }
 169
 170 void mmu_setup(void)
 171 {
 172         final_mmu_setup();
 173 }
 174
 175 /*
 176  * This function is called from common/board_r.c.
 177  * It recreates MMU table in main memory.
 178  */
 179 void enable_caches(void)
 180 {
 181         mmu_setup();
 182         __asm_invalidate_tlb_all();
 183         icache_enable();
 184         dcache_enable();
 185 }
 186 #endif
 187
 188 static inline u32 initiator_type(u32 cluster, int init_id)
 189 {
 190         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 191         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 192         u32 type = 0;
 193
 194         type = gur_in32(&gur->tp_ityp[idx]);
 195         if (type & TP_ITYP_AV)
 196                 return type;
 197
 198         return 0;
 199 }
 200
 201 u32 cpu_mask(void)
 202 {
 203         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 204         int i = 0, count = 0;
 205         u32 cluster, type, mask = 0;
 206
 207         do {
 208                 int j;
 209
 210                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 211                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 212                         type = initiator_type(cluster, j);
 213                         if (type) {
 214                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 215                                         mask |= 1 << count;
 216                                 count++;
 217                         }
 218                 }
 219                 i++;
 220         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 221
 222         return mask;
 223 }
 224
 225 /*
 226  * Return the number of cores on this SOC.
 227  */
 228 int cpu_numcores(void)
 229 {
 230         return hweight32(cpu_mask());
 231 }
 232
 233 int fsl_qoriq_core_to_cluster(unsigned int core)
 234 {
 235         struct ccsr_gur __iomem *gur =
 236                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 237         int i = 0, count = 0;
 238         u32 cluster;
 239
 240         do {
 241                 int j;
 242
 243                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 244                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 245                         if (initiator_type(cluster, j)) {
 246                                 if (count == core)
 247                                         return i;
 248                                 count++;
 249                         }
 250                 }
 251                 i++;
 252         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 253
 254         return -1;      /* cannot identify the cluster */
 255 }
 256
 257 u32 fsl_qoriq_core_to_type(unsigned int core)
 258 {
 259         struct ccsr_gur __iomem *gur =
 260                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 261         int i = 0, count = 0;
 262         u32 cluster, type;
 263
 264         do {
 265                 int j;
 266
 267                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 268                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 269                         type = initiator_type(cluster, j);
 270                         if (type) {
 271                                 if (count == core)
 272                                         return type;
 273                                 count++;
 274                         }
 275                 }
 276                 i++;
 277         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 278
 279         return -1;      /* cannot identify the cluster */
 280 }
 281
 282 uint get_svr(void)
 283 {
 284         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 285
 286         return gur_in32(&gur->svr);
 287 }
 288
 289 #ifdef CONFIG_DISPLAY_CPUINFO
 290 int print_cpuinfo(void)
 291 {
 292         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 293         struct sys_info sysinfo;
 294         char buf[32];
 295         unsigned int i, core;
 296         u32 type, rcw, svr = gur_in32(&gur->svr);
 297
 298         puts("SoC: ");
 299
 300         cpu_name(buf);
 301         printf(" %s (0x%x)\n", buf, svr);
 302         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 303         get_sys_info(&sysinfo);
 304         puts("Clock Configuration:");
 305         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
 306                 if (!(i % 3))
 307                         puts("\n       ");
 308                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
 309                 printf("CPU%d(%s):%-4s MHz  ", core,
 310                        type == TY_ITYP_VER_A7 ? "A7 " :
 311                        (type == TY_ITYP_VER_A53 ? "A53" :
 312                        (type == TY_ITYP_VER_A57 ? "A57" :
 313                        (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
 314                        strmhz(buf, sysinfo.freq_processor[core]));
 315         }
 316         printf("\n       Bus:      %-4s MHz  ",
 317                strmhz(buf, sysinfo.freq_systembus));
 318         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
 319 #ifdef CONFIG_SYS_DPAA_FMAN
 320         printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
 321 #endif
 322 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 323         if (soc_has_dp_ddr()) {
 324                 printf("     DP-DDR:   %-4s MT/s",
 325                        strmhz(buf, sysinfo.freq_ddrbus2));
 326         }
 327 #endif
 328         puts("\n");
 329
 330         /*
 331          * Display the RCW, so that no one gets confused as to what RCW
 332          * we're actually using for this boot.
 333          */
 334         puts("Reset Configuration Word (RCW):");
 335         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
 336                 rcw = gur_in32(&gur->rcwsr[i]);
 337                 if ((i % 4) == 0)
 338                         printf("\n       %08x:", i * 4);
 339                 printf(" %08x", rcw);
 340         }
 341         puts("\n");
 342
 343         return 0;
 344 }
 345 #endif
 346
 347 #ifdef CONFIG_FSL_ESDHC
 348 int cpu_mmc_init(bd_t *bis)
 349 {
 350         return fsl_esdhc_mmc_init(bis);
 351 }
 352 #endif
 353
 354 int cpu_eth_init(bd_t *bis)
 355 {
 356         int error = 0;
 357
 358 #ifdef CONFIG_FSL_MC_ENET
 359         error = fsl_mc_ldpaa_init(bis);
 360 #endif
 361 #ifdef CONFIG_FMAN_ENET
 362         fm_standard_init(bis);
 363 #endif
 364         return error;
 365 }
 366
 367 int arch_early_init_r(void)
 368 {
 369 #ifdef CONFIG_MP
 370         int rv = 1;
 371         u32 psci_ver = 0xffffffff;
 372 #endif
 373
 374 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 375         erratum_a009635();
 376 #endif
 377
 378 #ifdef CONFIG_MP
 379 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
 380         /* Check the psci version to determine if the psci is supported */
 381         psci_ver = sec_firmware_support_psci_version();
 382 #endif
 383         if (psci_ver == 0xffffffff) {
 384                 rv = fsl_layerscape_wake_seconday_cores();
 385                 if (rv)
 386                         printf("Did not wake secondary cores\n");
 387         }
 388 #endif
 389
 390 #ifdef CONFIG_SYS_HAS_SERDES
 391         fsl_serdes_init();
 392 #endif
 393 #ifdef CONFIG_FMAN_ENET
 394         fman_enet_init();
 395 #endif
 396         return 0;
 397 }
 398
 399 int timer_init(void)
 400 {
 401         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 402 #ifdef CONFIG_FSL_LSCH3
 403         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 404 #endif
 405 #ifdef CONFIG_LS2080A
 406         u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
 407 #endif
 408 #ifdef COUNTER_FREQUENCY_REAL
 409         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 410
 411         /* Update with accurate clock frequency */
 412         asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
 413 #endif
 414
 415 #ifdef CONFIG_FSL_LSCH3
 416         /* Enable timebase for all clusters.
 417          * It is safe to do so even some clusters are not enabled.
 418          */
 419         out_le32(cltbenr, 0xf);
 420 #endif
 421
 422 #ifdef CONFIG_LS2080A
 423         /*
 424          * In certain Layerscape SoCs, the clock for each core's
 425          * has an enable bit in the PMU Physical Core Time Base Enable
 426          * Register (PCTBENR), which allows the watchdog to operate.
 427          */
 428         setbits_le32(pctbenr, 0xff);
 429 #endif
 430
 431         /* Enable clock for timer
 432          * This is a global setting.
 433          */
 434         out_le32(cntcr, 0x1);
 435
 436         return 0;
 437 }
 438
 439 void reset_cpu(ulong addr)
 440 {
 441         u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
 442         u32 val;
 443
 444         /* Raise RESET_REQ_B */
 445         val = scfg_in32(rstcr);
 446         val |= 0x02;
 447         scfg_out32(rstcr, val);
 448 }
 449
 450 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
 451 {
 452         phys_size_t ram_top = ram_size;
 453
 454 #ifdef CONFIG_SYS_MEM_TOP_HIDE
 455 #error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
 456 #endif
 457 /* Carve the Debug Server private DRAM block from the end of DRAM */
 458 #ifdef CONFIG_FSL_DEBUG_SERVER
 459         ram_top -= debug_server_get_dram_block_size();
 460 #endif
 461
 462 /* Carve the MC private DRAM block from the end of DRAM */
 463 #ifdef CONFIG_FSL_MC_ENET
 464         ram_top -= mc_get_dram_block_size();
 465         ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
 466 #endif
 467
 468         return ram_top;
 469 }