arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc

   1 SoC overview
   2
   3         1. LS1043A
   4         2. LS1088A
   5         3. LS2080A
   6         4. LS1012A
   7         5. LS1046A
   8         6. LS2088A
   9         7. LS2081A
  10
  11 LS1043A
  12 ---------
  13 The LS1043A integrated multicore processor combines four ARM Cortex-A53
  14 processor cores with datapath acceleration optimized for L2/3 packet
  15 processing, single pass security offload and robust traffic management
  16 and quality of service.
  17
  18 The LS1043A SoC includes the following function and features:
  19  - Four 64-bit ARM Cortex-A53 CPUs
  20  - 1 MB unified L2 Cache
  21  - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
  22    support
  23  - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
  24    the following functions:
  25    - Packet parsing, classification, and distribution (FMan)
  26    - Queue management for scheduling, packet sequencing, and congestion
  27      management (QMan)
  28    - Hardware buffer management for buffer allocation and de-allocation (BMan)
  29    - Cryptography acceleration (SEC)
  30  - Ethernet interfaces by FMan
  31    - Up to 1 x XFI supporting 10G interface
  32    - Up to 1 x QSGMII
  33    - Up to 4 x SGMII supporting 1000Mbps
  34    - Up to 2 x SGMII supporting 2500Mbps
  35    - Up to 2 x RGMII supporting 1000Mbps
  36  - High-speed peripheral interfaces
  37    - Three PCIe 2.0 controllers, one supporting x4 operation
  38    - One serial ATA (SATA 3.0) controllers
  39  - Additional peripheral interfaces
  40    - Three high-speed USB 3.0 controllers with integrated PHY
  41    - Enhanced secure digital host controller (eSDXC/eMMC)
  42    - Quad Serial Peripheral Interface (QSPI) Controller
  43    - Serial peripheral interface (SPI) controller
  44    - Four I2C controllers
  45    - Two DUARTs
  46    - Integrated flash controller supporting NAND and NOR flash
  47  - QorIQ platform's trust architecture 2.1
  48
  49 LS1088A
  50 --------
  51 The QorIQ LS1088A processor is built on the Layerscape
  52 architecture combining eight ARM A53 processor cores
  53 with advanced, high-performance datapath acceleration
  54 and networks, peripheral interfaces required for
  55 networking, wireless infrastructure, and general-purpose
  56 embedded applications.
  57
  58 LS1088A is compliant with the Layerscape Chassis Generation 3.
  59
  60 Features summary:
  61  - 8 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
  62  - Cores are in 2 cluster of 4-cores each
  63  - 1MB L2 - Cache per cluster
  64  - Cache coherent interconnect (CCI-400)
  65  - 1 64-bit DDR4 SDRAM memory controller with ECC
  66  - Data path acceleration architecture 2.0 (DPAA2)
  67  - 4-Lane 10GHz SerDes comprising of WRIOP
  68  - 4-Lane 10GHz SerDes comprising of PCI, SATA, uQE(TDM/HLDC/UART)
  69  - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
  70  - QSPI, SPI, IFC2.0 supporting NAND, NOR flash
  71  - 3 PCIe3.0 , 1 SATA3.0, 2 USB3.0, 1 SDXC, 2 DUARTs etc
  72  - 2 DUARTs
  73  - 4 I2C, GPIO
  74  - Thermal monitor unit(TMU)
  75  - 4 Flextimers and 1 generic timer
  76  - Support for hardware virtualization and partitioning enforcement
  77  - QorIQ platform's trust architecture 3.0
  78  - Service processor (SP) provides pre-boot initialization and secure-boot
  79    capabilities
  80
  81 LS2080A
  82 --------
  83 The LS2080A integrated multicore processor combines eight ARM Cortex-A57
  84 processor cores with high-performance data path acceleration logic and network
  85 and peripheral bus interfaces required for networking, telecom/datacom,
  86 wireless infrastructure, and mil/aerospace applications.
  87
  88 The LS2080A SoC includes the following function and features:
  89
  90  - Eight 64-bit ARM Cortex-A57 CPUs
  91  - 1 MB platform cache with ECC
  92  - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
  93  - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
  94   the AIOP
  95  - Data path acceleration architecture (DPAA2) incorporating acceleration for
  96  the following functions:
  97    - Packet parsing, classification, and distribution (WRIOP)
  98    - Queue and Hardware buffer management for scheduling, packet sequencing, and
  99      congestion management, buffer allocation and de-allocation (QBMan)
 100    - Cryptography acceleration (SEC) at up to 10 Gbps
 101    - RegEx pattern matching acceleration (PME) at up to 10 Gbps
 102    - Decompression/compression acceleration (DCE) at up to 20 Gbps
 103    - Accelerated I/O processing (AIOP) at up to 20 Gbps
 104    - QDMA engine
 105  - 16 SerDes lanes at up to 10.3125 GHz
 106  - Ethernet interfaces
 107    - Up to eight 10 Gbps Ethernet MACs
 108    - Up to eight 1 / 2.5 Gbps Ethernet MACs
 109  - High-speed peripheral interfaces
 110    - Four PCIe 3.0 controllers, one supporting SR-IOV
 111  - Additional peripheral interfaces
 112    - Two serial ATA (SATA 3.0) controllers
 113    - Two high-speed USB 3.0 controllers with integrated PHY
 114    - Enhanced secure digital host controller (eSDXC/eMMC)
 115    - Serial peripheral interface (SPI) controller
 116    - Quad Serial Peripheral Interface (QSPI) Controller
 117    - Four I2C controllers
 118    - Two DUARTs
 119    - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
 120  - Support for hardware virtualization and partitioning enforcement
 121  - QorIQ platform's trust architecture 3.0
 122  - Service processor (SP) provides pre-boot initialization and secure-boot
 123   capabilities
 124
 125 LS1012A
 126 --------
 127 The LS1012A features an advanced 64-bit ARM v8 Cortex-
 128 A53 processor, with 32 KB of parity protected L1-I cache,
 129 32 KB of ECC protected L1-D cache, as well as 256 KB of
 130 ECC protected L2 cache.
 131
 132 The LS1012A SoC includes the following function and features:
 133  - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
 134  - ARM v8 cryptography extensions
 135  - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
 136     16-/8-bit operation (no ECC support)
 137  - ARM core-link CCI-400 cache coherent interconnect
 138  - Packet Forwarding Engine (PFE)
 139  - Cryptography acceleration (SEC)
 140  - Ethernet interfaces supported by PFE:
 141  - One Configurable x3 SerDes:
 142     Two Serdes PLLs supported for usage by any SerDes data lane
 143     Support for up to 6 GBaud operation
 144  - High-speed peripheral interfaces:
 145      - One PCI Express Gen2 controller, supporting x1 operation
 146      - One serial ATA (SATA Gen 3.0) controller
 147      - One USB 3.0/2.0 controller with integrated PHY
 148      - One USB 2.0 controller with ULPI interface. .
 149  - Additional peripheral interfaces:
 150     - One quad serial peripheral interface (QuadSPI) controller
 151     - One serial peripheral interface (SPI) controller
 152     - Two enhanced secure digital host controllers
 153     - Two I2C controllers
 154     - One 16550 compliant DUART (two UART interfaces)
 155     - Two general purpose IOs (GPIO)
 156     - Two FlexTimers
 157     - Five synchronous audio interfaces (SAI)
 158     - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
 159     - Single-source clocking solution enabling generation of core, platform,
 160     DDR, SerDes, and USB clocks from a single external crystal and internal
 161     crystaloscillator
 162     - Thermal monitor unit (TMU) with +/- 3C accuracy
 163     - Two WatchDog timers
 164     - ARM generic timer
 165  - QorIQ platform's trust architecture 2.1
 166
 167 LS1046A
 168 --------
 169 The LS1046A integrated multicore processor combines four ARM Cortex-A72
 170 processor cores with datapath acceleration optimized for L2/3 packet
 171 processing, single pass security offload and robust traffic management
 172 and quality of service.
 173
 174 The LS1046A SoC includes the following function and features:
 175  - Four 64-bit ARM Cortex-A72 CPUs
 176  - 2 MB unified L2 Cache
 177  - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
 178    support
 179  - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
 180    the following functions:
 181    - Packet parsing, classification, and distribution (FMan)
 182    - Queue management for scheduling, packet sequencing, and congestion
 183      management (QMan)
 184    - Hardware buffer management for buffer allocation and de-allocation (BMan)
 185    - Cryptography acceleration (SEC)
 186  - Two Configurable x4 SerDes
 187    - Two PLLs per four-lane SerDes
 188    - Support for 10G operation
 189  - Ethernet interfaces by FMan
 190    - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
 191    - Up to 1 x QSGMII (MAC 5, 6, 10, 1)
 192    - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
 193    - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
 194    - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
 195  - High-speed peripheral interfaces
 196    - Three PCIe 3.0 controllers, one supporting x4 operation
 197    - One serial ATA (SATA 3.0) controllers
 198  - Additional peripheral interfaces
 199    - Three high-speed USB 3.0 controllers with integrated PHY
 200    - Enhanced secure digital host controller (eSDXC/eMMC)
 201    - Quad Serial Peripheral Interface (QSPI) Controller
 202    - Serial peripheral interface (SPI) controller
 203    - Four I2C controllers
 204    - Two DUARTs
 205    - Integrated flash controller (IFC) supporting NAND and NOR flash
 206  - QorIQ platform's trust architecture 2.1
 207
 208 LS2088A
 209 --------
 210 The LS2088A integrated multicore processor combines eight ARM Cortex-A72
 211 processor cores with high-performance data path acceleration logic and network
 212 and peripheral bus interfaces required for networking, telecom/datacom,
 213 wireless infrastructure, and mil/aerospace applications.
 214
 215 The LS2088A SoC includes the following function and features:
 216
 217  - Eight 64-bit ARM Cortex-A72 CPUs
 218  - 1 MB platform cache with ECC
 219  - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
 220  - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
 221    the AIOP
 222  - Data path acceleration architecture (DPAA2) incorporating acceleration for
 223    the following functions:
 224    - Packet parsing, classification, and distribution (WRIOP)
 225    - Queue and Hardware buffer management for scheduling, packet sequencing, and
 226      congestion management, buffer allocation and de-allocation (QBMan)
 227    - Cryptography acceleration (SEC) at up to 10 Gbps
 228    - RegEx pattern matching acceleration (PME) at up to 10 Gbps
 229    - Decompression/compression acceleration (DCE) at up to 20 Gbps
 230    - Accelerated I/O processing (AIOP) at up to 20 Gbps
 231    - QDMA engine
 232  - 16 SerDes lanes at up to 10.3125 GHz
 233  - Ethernet interfaces
 234    - Up to eight 10 Gbps Ethernet MACs
 235    - Up to eight 1 / 2.5 Gbps Ethernet MACs
 236  - High-speed peripheral interfaces
 237    - Four PCIe 3.0 controllers, one supporting SR-IOV
 238  - Additional peripheral interfaces
 239    - Two serial ATA (SATA 3.0) controllers
 240    - Two high-speed USB 3.0 controllers with integrated PHY
 241    - Enhanced secure digital host controller (eSDXC/eMMC)
 242    - Serial peripheral interface (SPI) controller
 243    - Quad Serial Peripheral Interface (QSPI) Controller
 244    - Four I2C controllers
 245    - Two DUARTs
 246    - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
 247  - Support for hardware virtualization and partitioning enforcement
 248  - QorIQ platform's trust architecture 3.0
 249  - Service processor (SP) provides pre-boot initialization and secure-boot
 250  capabilities
 251
 252 LS2088A SoC has 3 more similar SoC personalities
 253 1)LS2048A, few difference w.r.t. LS2088A:
 254        a) Four 64-bit ARM v8 Cortex-A72 CPUs
 255
 256 2)LS2084A, few difference w.r.t. LS2088A:
 257        a) No AIOP
 258        b) No 32-bit DDR3 SDRAM memory
 259        c) 5 * 1/10G + 5 *1G WRIOP
 260        d) No L2 switch
 261
 262 3)LS2044A, few difference w.r.t. LS2084A:
 263        a) Four 64-bit ARM v8 Cortex-A72 CPUs
 264
 265 LS2081A
 266 --------
 267 LS2081A is 40-pin derivative of LS2084A.
 268 So feature-wise it is same as LS2084A.
 269 Refer to LS2084A(LS2088A) section above for details.
 270
 271 It has one more similar SoC personality
 272 1)LS2041A, few difference w.r.t. LS2081A:
 273        a) Four 64-bit ARM v8 Cortex-A72 CPUs