2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/errno.h>
10 #include <asm/arch/fsl_serdes.h>
11 #include <asm/arch/soc.h>
12 #include <fsl-mc/ldpaa_wriop.h>
14 #ifdef CONFIG_SYS_FSL_SRDS_1
15 static u8 serdes1_prtcl_map
[SERDES_PRCTL_COUNT
];
17 #ifdef CONFIG_SYS_FSL_SRDS_2
18 static u8 serdes2_prtcl_map
[SERDES_PRCTL_COUNT
];
21 #ifdef CONFIG_FSL_MC_ENET
22 int xfi_dpmac
[XFI8
+ 1];
23 int sgmii_dpmac
[SGMII16
+ 1];
26 int is_serdes_configured(enum srds_prtcl device
)
30 #ifdef CONFIG_SYS_FSL_SRDS_1
31 if (!serdes1_prtcl_map
[NONE
])
34 ret
|= serdes1_prtcl_map
[device
];
36 #ifdef CONFIG_SYS_FSL_SRDS_2
37 if (!serdes2_prtcl_map
[NONE
])
40 ret
|= serdes2_prtcl_map
[device
];
46 int serdes_get_first_lane(u32 sd
, enum srds_prtcl device
)
48 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
49 u32 cfg
= gur_in32(&gur
->rcwsr
[28]);
53 #ifdef CONFIG_SYS_FSL_SRDS_1
55 cfg
&= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
;
56 cfg
>>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
;
59 #ifdef CONFIG_SYS_FSL_SRDS_2
61 cfg
&= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
;
62 cfg
>>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
;
66 printf("invalid SerDes%d\n", sd
);
69 /* Is serdes enabled at all? */
73 for (i
= 0; i
< SRDS_MAX_LANES
; i
++) {
74 if (serdes_get_prtcl(sd
, cfg
, i
) == device
)
81 void serdes_init(u32 sd
, u32 sd_addr
, u32 sd_prctl_mask
, u32 sd_prctl_shift
,
82 u8 serdes_prtcl_map
[SERDES_PRCTL_COUNT
])
84 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
88 if (serdes_prtcl_map
[NONE
])
91 memset(serdes_prtcl_map
, 0, sizeof(u8
) * SERDES_PRCTL_COUNT
);
93 cfg
= gur_in32(&gur
->rcwsr
[28]) & sd_prctl_mask
;
94 cfg
>>= sd_prctl_shift
;
95 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd
+ 1, cfg
, cfg
);
97 if (!is_serdes_prtcl_valid(sd
, cfg
))
98 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd
+ 1, cfg
);
100 for (lane
= 0; lane
< SRDS_MAX_LANES
; lane
++) {
101 enum srds_prtcl lane_prtcl
= serdes_get_prtcl(sd
, cfg
, lane
);
102 if (unlikely(lane_prtcl
>= SERDES_PRCTL_COUNT
))
103 debug("Unknown SerDes lane protocol %d\n", lane_prtcl
);
105 serdes_prtcl_map
[lane_prtcl
] = 1;
106 #ifdef CONFIG_FSL_MC_ENET
107 switch (lane_prtcl
) {
109 wriop_init_dpmac(sd
, 5, (int)lane_prtcl
);
110 wriop_init_dpmac(sd
, 6, (int)lane_prtcl
);
111 wriop_init_dpmac(sd
, 7, (int)lane_prtcl
);
112 wriop_init_dpmac(sd
, 8, (int)lane_prtcl
);
115 wriop_init_dpmac(sd
, 1, (int)lane_prtcl
);
116 wriop_init_dpmac(sd
, 2, (int)lane_prtcl
);
117 wriop_init_dpmac(sd
, 3, (int)lane_prtcl
);
118 wriop_init_dpmac(sd
, 4, (int)lane_prtcl
);
121 wriop_init_dpmac(sd
, 13, (int)lane_prtcl
);
122 wriop_init_dpmac(sd
, 14, (int)lane_prtcl
);
123 wriop_init_dpmac(sd
, 15, (int)lane_prtcl
);
124 wriop_init_dpmac(sd
, 16, (int)lane_prtcl
);
127 wriop_init_dpmac(sd
, 9, (int)lane_prtcl
);
128 wriop_init_dpmac(sd
, 10, (int)lane_prtcl
);
129 wriop_init_dpmac(sd
, 11, (int)lane_prtcl
);
130 wriop_init_dpmac(sd
, 12, (int)lane_prtcl
);
133 if (lane_prtcl
>= XFI1
&& lane_prtcl
<= XFI8
)
135 xfi_dpmac
[lane_prtcl
],
138 if (lane_prtcl
>= SGMII1
&&
139 lane_prtcl
<= SGMII16
)
140 wriop_init_dpmac(sd
, sgmii_dpmac
[
149 /* Set the first element to indicate serdes has been initialized */
150 serdes_prtcl_map
[NONE
] = 1;
153 void fsl_serdes_init(void)
155 #ifdef CONFIG_FSL_MC_ENET
158 for (i
= XFI1
, j
= 1; i
<= XFI8
; i
++, j
++)
161 for (i
= SGMII1
, j
= 1; i
<= SGMII16
; i
++, j
++)
165 #ifdef CONFIG_SYS_FSL_SRDS_1
166 serdes_init(FSL_SRDS_1
,
167 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
,
168 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
,
169 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
,
172 #ifdef CONFIG_SYS_FSL_SRDS_2
173 serdes_init(FSL_SRDS_2
,
174 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
+ FSL_SRDS_2
* 0x10000,
175 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
,
176 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
,