arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <asm/arch/fsl_serdes.h>
   8
   9 struct serdes_config {
  10         u8 protocol;
  11         u8 lanes[SRDS_MAX_LANES];
  12 };
  13
  14 static struct serdes_config serdes1_cfg_tbl[] = {
  15         /* SerDes 1 */
  16         {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
  17         {0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
  18         {0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
  19                 SGMII1 } },
  20         {0x09, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
  21                 SGMII1 } },
  22         {0x0A, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
  23                 SGMII1 } },
  24         {0x0C, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
  25                 SGMII1 } },
  26         {0x0E, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
  27                 SGMII1 } },
  28         {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
  29         {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
  30         {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
  31         {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1  } },
  32         {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1  } },
  33         {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B,
  34                 QSGMII_A} },
  35         {0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
  36         {0x39, {SGMII8, SGMII7, SGMII6, PCIE2, SGMII4, SGMII3, SGMII2,
  37                 PCIE1 } },
  38         {0x3B, {XFI8, XFI7, XFI6, PCIE2, XFI4, XFI3, XFI2, PCIE1 } },
  39         {0x4B, {PCIE2, PCIE2, PCIE2, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
  40         {0x4C, {XFI8, XFI7, XFI6, XFI5, PCIE1, PCIE1, PCIE1, PCIE1 } },
  41         {0x4D, {SGMII8, SGMII7, PCIE2, PCIE2, SGMII4, SGMII3, PCIE1, PCIE1 } },
  42                 {}
  43 };
  44 static struct serdes_config serdes2_cfg_tbl[] = {
  45         /* SerDes 2 */
  46         {0x07, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
  47                 SGMII16 } },
  48         {0x09, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
  49                 SGMII16 } },
  50         {0x0A, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
  51                 SGMII16 } },
  52         {0x0C, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
  53                 SGMII16 } },
  54         {0x0E, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
  55                 SGMII16 } },
  56         {0x3D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
  57         {0x3E, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
  58         {0x3F, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
  59         {0x40, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
  60         {0x41, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
  61         {0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
  62         {0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
  63         {0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
  64         {0x45, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4,
  65                 PCIE4 } },
  66         {0x47, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
  67                 SGMII16 } },
  68         {0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
  69                 SATA2 } },
  70         {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
  71                 SATA2 } },
  72         {0x51, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
  73         {0x57, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII15, SGMII16 } },
  74         {}
  75 };
  76
  77 static struct serdes_config *serdes_cfg_tbl[] = {
  78         serdes1_cfg_tbl,
  79         serdes2_cfg_tbl,
  80 };
  81
  82 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
  83 {
  84         struct serdes_config *ptr;
  85
  86         if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  87                 return 0;
  88
  89         ptr = serdes_cfg_tbl[serdes];
  90         while (ptr->protocol) {
  91                 if (ptr->protocol == cfg)
  92                         return ptr->lanes[lane];
  93                 ptr++;
  94         }
  95
  96         return 0;
  97 }
  98
  99 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
 100 {
 101         int i;
 102         struct serdes_config *ptr;
 103
 104         if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
 105                 return 0;
 106
 107         ptr = serdes_cfg_tbl[serdes];
 108         while (ptr->protocol) {
 109                 if (ptr->protocol == prtcl)
 110                         break;
 111                 ptr++;
 112         }
 113
 114         if (!ptr->protocol)
 115                 return 0;
 116
 117         for (i = 0; i < SRDS_MAX_LANES; i++) {
 118                 if (ptr->lanes[i] != NONE)
 119                         return 1;
 120         }
 121
 122         return 0;
 123 }