2 * Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/soc.h>
13 #include <asm/global_data.h>
14 #include <asm/arch-fsl-layerscape/config.h>
16 DECLARE_GLOBAL_DATA_PTR
;
18 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
20 * This erratum requires setting a value to eddrtqcr1 to
21 * optimal the DDR performance.
23 static void erratum_a008336(void)
27 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
28 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
29 eddrtqcr1
= (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR
+ 0x800;
30 out_le32(eddrtqcr1
, 0x63b30002);
32 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
33 eddrtqcr1
= (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR
+ 0x800;
34 out_le32(eddrtqcr1
, 0x63b30002);
40 * This erratum requires a register write before being Memory
41 * controller 3 being enabled.
43 static void erratum_a008514(void)
47 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
48 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
49 eddrtqcr1
= (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR
+ 0x800;
50 out_le32(eddrtqcr1
, 0x63b20002);
54 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
55 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
57 static unsigned long get_internval_val_mhz(void)
59 char *interval
= getenv(PLATFORM_CYCLE_ENV_VAR
);
61 * interval is the number of platform cycles(MHz) between
62 * wake up events generated by EPU.
64 ulong interval_mhz
= get_bus_freq(0) / (1000 * 1000);
67 interval_mhz
= simple_strtoul(interval
, NULL
, 10);
72 void erratum_a009635(void)
75 unsigned long interval_mhz
= get_internval_val_mhz();
80 val
= in_le32(DCSR_CGACRE5
);
81 writel(val
| 0x00000200, DCSR_CGACRE5
);
83 val
= in_le32(EPU_EPCMPR5
);
84 writel(interval_mhz
, EPU_EPCMPR5
);
85 val
= in_le32(EPU_EPCCR5
);
86 writel(val
| 0x82820000, EPU_EPCCR5
);
87 val
= in_le32(EPU_EPSMCR5
);
88 writel(val
| 0x002f0000, EPU_EPSMCR5
);
89 val
= in_le32(EPU_EPECR5
);
90 writel(val
| 0x20000000, EPU_EPECR5
);
91 val
= in_le32(EPU_EPGCR
);
92 writel(val
| 0x80000000, EPU_EPGCR
);
94 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
96 static void erratum_a008751(void)
98 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751
99 u32 __iomem
*scfg
= (u32 __iomem
*)SCFG_BASE
;
101 writel(0x27672b2a, scfg
+ SCFG_USB3PRM1CR
/ 4);
105 static void erratum_rcw_src(void)
107 #if defined(CONFIG_SPL)
108 u32 __iomem
*dcfg_ccsr
= (u32 __iomem
*)DCFG_BASE
;
109 u32 __iomem
*dcfg_dcsr
= (u32 __iomem
*)DCFG_DCSR_BASE
;
112 val
= in_le32(dcfg_ccsr
+ DCFG_PORSR1
/ 4);
113 val
&= ~DCFG_PORSR1_RCW_SRC
;
114 val
|= DCFG_PORSR1_RCW_SRC_NOR
;
115 out_le32(dcfg_dcsr
+ DCFG_DCSR_PORCR1
/ 4, val
);
119 #define I2C_DEBUG_REG 0x6
120 #define I2C_GLITCH_EN 0x8
122 * This erratum requires setting glitch_en bit to enable
123 * digital glitch filter to improve clock stability.
125 static void erratum_a009203(void)
128 #ifdef CONFIG_SYS_I2C
129 #ifdef I2C1_BASE_ADDR
130 ptr
= (u8 __iomem
*)(I2C1_BASE_ADDR
+ I2C_DEBUG_REG
);
132 writeb(I2C_GLITCH_EN
, ptr
);
134 #ifdef I2C2_BASE_ADDR
135 ptr
= (u8 __iomem
*)(I2C2_BASE_ADDR
+ I2C_DEBUG_REG
);
137 writeb(I2C_GLITCH_EN
, ptr
);
139 #ifdef I2C3_BASE_ADDR
140 ptr
= (u8 __iomem
*)(I2C3_BASE_ADDR
+ I2C_DEBUG_REG
);
142 writeb(I2C_GLITCH_EN
, ptr
);
144 #ifdef I2C4_BASE_ADDR
145 ptr
= (u8 __iomem
*)(I2C4_BASE_ADDR
+ I2C_DEBUG_REG
);
147 writeb(I2C_GLITCH_EN
, ptr
);
152 void fsl_lsch3_early_init_f(void)
156 init_early_memctl_regs(); /* tighten IFC timing */
162 #ifdef CONFIG_SCSI_AHCI_PLAT
165 struct ccsr_ahci __iomem
*ccsr_ahci
;
167 ccsr_ahci
= (void *)CONFIG_SYS_SATA2
;
168 out_le32(&ccsr_ahci
->ppcfg
, AHCI_PORT_PHY_1_CFG
);
169 out_le32(&ccsr_ahci
->ptc
, AHCI_PORT_TRANS_CFG
);
171 ccsr_ahci
= (void *)CONFIG_SYS_SATA1
;
172 out_le32(&ccsr_ahci
->ppcfg
, AHCI_PORT_PHY_1_CFG
);
173 out_le32(&ccsr_ahci
->ptc
, AHCI_PORT_TRANS_CFG
);
175 ahci_init((void __iomem
*)CONFIG_SYS_SATA1
);
182 #elif defined(CONFIG_LS1043A)
183 #ifdef CONFIG_SCSI_AHCI_PLAT
186 struct ccsr_ahci __iomem
*ccsr_ahci
= (void *)CONFIG_SYS_SATA
;
188 out_le32(&ccsr_ahci
->ppcfg
, AHCI_PORT_PHY_1_CFG
);
189 out_le32(&ccsr_ahci
->pp2c
, AHCI_PORT_PHY_2_CFG
);
190 out_le32(&ccsr_ahci
->pp3c
, AHCI_PORT_PHY_3_CFG
);
191 out_le32(&ccsr_ahci
->ptc
, AHCI_PORT_TRANS_CFG
);
193 ahci_init((void __iomem
*)CONFIG_SYS_SATA
);
200 static void erratum_a009929(void)
202 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
203 struct ccsr_gur
*gur
= (void *)CONFIG_SYS_FSL_GUTS_ADDR
;
204 u32 __iomem
*dcsr_cop_ccp
= (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR
;
205 u32 rstrqmr1
= gur_in32(&gur
->rstrqmr1
);
207 rstrqmr1
|= 0x00000400;
208 gur_out32(&gur
->rstrqmr1
, rstrqmr1
);
209 writel(0x01000000, dcsr_cop_ccp
);
213 void fsl_lsch2_early_init_f(void)
215 struct ccsr_cci400
*cci
= (struct ccsr_cci400
*)CONFIG_SYS_CCI400_ADDR
;
216 struct ccsr_scfg
*scfg
= (struct ccsr_scfg
*)CONFIG_SYS_FSL_SCFG_ADDR
;
218 #ifdef CONFIG_FSL_IFC
219 init_early_memctl_regs(); /* tighten IFC timing */
222 /* Make SEC reads and writes snoopable */
223 setbits_be32(&scfg
->snpcnfgcr
, SCFG_SNPCNFGCR_SECRDSNP
|
224 SCFG_SNPCNFGCR_SECWRSNP
);
227 * Enable snoop requests and DVM message requests for
228 * Slave insterface S4 (A53 core cluster)
230 out_le32(&cci
->slave
[4].snoop_ctrl
,
231 CCI400_DVM_MESSAGE_REQ_EN
| CCI400_SNOOP_REQ_EN
);
238 #ifdef CONFIG_BOARD_LATE_INIT
239 int board_late_init(void)
241 #ifdef CONFIG_SCSI_AHCI_PLAT