arch/arm/cpu/armv8/fsl-layerscape/soc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014-2015 Freescale Semiconductor
   4  * Copyright 2019-2021 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <clock_legacy.h>
   9 #include <cpu_func.h>
  10 #include <env.h>
  11 #include <fsl_immap.h>
  12 #include <fsl_ifc.h>
  13 #include <init.h>
  14 #include <linux/sizes.h>
  15 #include <log.h>
  16 #include <asm/arch/fsl_serdes.h>
  17 #include <asm/arch/soc.h>
  18 #include <asm/cache.h>
  19 #include <asm/io.h>
  20 #include <asm/global_data.h>
  21 #include <asm/arch-fsl-layerscape/config.h>
  22 #include <asm/arch-fsl-layerscape/ns_access.h>
  23 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  24 #include <asm/gic-v3.h>
  25 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  26 #include <fsl_csu.h>
  27 #endif
  28 #ifdef CONFIG_SYS_FSL_DDR
  29 #include <fsl_ddr_sdram.h>
  30 #include <fsl_ddr.h>
  31 #endif
  32 #ifdef CONFIG_CHAIN_OF_TRUST
  33 #include <fsl_validate.h>
  34 #endif
  35 #include <fsl_immap.h>
  36 #include <dm.h>
  37 #include <dm/device_compat.h>
  38 #include <linux/err.h>
  39 #ifdef CONFIG_GIC_V3_ITS
  40 DECLARE_GLOBAL_DATA_PTR;
  41 #endif
  42
  43 #ifdef CONFIG_GIC_V3_ITS
  44 int ls_gic_rd_tables_init(void *blob)
  45 {
  46         struct fdt_memory lpi_base;
  47         fdt_addr_t addr;
  48         fdt_size_t size;
  49         int offset, ret;
  50
  51         offset = fdt_path_offset(gd->fdt_blob, "/syscon@0x80000000");
  52         addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, offset, "reg",
  53                                                   0, &size, false);
  54
  55         lpi_base.start = addr;
  56         lpi_base.end = addr + size - 1;
  57         ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, false);
  58         if (ret) {
  59                 debug("%s: failed to add reserved memory\n", __func__);
  60                 return ret;
  61         }
  62
  63         ret = gic_lpi_tables_init();
  64         if (ret)
  65                 debug("%s: failed to init gic-lpi-tables\n", __func__);
  66
  67         return ret;
  68 }
  69 #endif
  70
  71 bool soc_has_dp_ddr(void)
  72 {
  73         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  74         u32 svr = gur_in32(&gur->svr);
  75
  76         /* LS2085A, LS2088A, LS2048A has DP_DDR */
  77         if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
  78             (SVR_SOC_VER(svr) == SVR_LS2088A) ||
  79             (SVR_SOC_VER(svr) == SVR_LS2048A))
  80                 return true;
  81
  82         return false;
  83 }
  84
  85 bool soc_has_aiop(void)
  86 {
  87         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  88         u32 svr = gur_in32(&gur->svr);
  89
  90         /* LS2085A has AIOP */
  91         if (SVR_SOC_VER(svr) == SVR_LS2085A)
  92                 return true;
  93
  94         return false;
  95 }
  96
  97 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
  98 {
  99         scfg_clrsetbits32(scfg + offset / 4,
 100                         0xF << 6,
 101                         SCFG_USB_TXVREFTUNE << 6);
 102 }
 103
 104 static void erratum_a009008(void)
 105 {
 106 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
 107         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
 108
 109 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
 110         defined(CONFIG_ARCH_LS1012A)
 111         set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
 112 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 113         set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
 114         set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
 115 #endif
 116 #elif defined(CONFIG_ARCH_LS2080A)
 117         set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
 118 #endif
 119 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 120 }
 121
 122 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
 123 {
 124         scfg_clrbits32(scfg + offset / 4,
 125                         SCFG_USB_SQRXTUNE_MASK << 23);
 126 }
 127
 128 static void erratum_a009798(void)
 129 {
 130 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
 131         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
 132
 133 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
 134         defined(CONFIG_ARCH_LS1012A)
 135         set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
 136 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 137         set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
 138         set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
 139 #endif
 140 #elif defined(CONFIG_ARCH_LS2080A)
 141         set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
 142 #endif
 143 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 144 }
 145
 146 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
 147         defined(CONFIG_ARCH_LS1012A)
 148 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
 149 {
 150         scfg_clrsetbits32(scfg + offset / 4,
 151                         0x7F << 9,
 152                         SCFG_USB_PCSTXSWINGFULL << 9);
 153 }
 154 #endif
 155
 156 static void erratum_a008997(void)
 157 {
 158 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
 159 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
 160         defined(CONFIG_ARCH_LS1012A)
 161         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
 162
 163         set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
 164 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 165         set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
 166         set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
 167 #endif
 168 #elif defined(CONFIG_ARCH_LS1028A)
 169         clrsetbits_le32(DCSR_BASE +  DCSR_USB_IOCR1,
 170                         0x7F << 11,
 171                         DCSR_USB_PCSTXSWINGFULL << 11);
 172 #endif
 173 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 174 }
 175
 176 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
 177         defined(CONFIG_ARCH_LS1012A)
 178
 179 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)      \
 180         out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);      \
 181         out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);      \
 182         out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);      \
 183         out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
 184
 185 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
 186         defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) || \
 187         defined(CONFIG_ARCH_LX2162A)
 188
 189 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)      \
 190         out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
 191         out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
 192         out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
 193         out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
 194
 195 #endif
 196
 197 static void erratum_a009007(void)
 198 {
 199 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
 200         defined(CONFIG_ARCH_LS1012A)
 201         void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
 202
 203         PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
 204 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 205         usb_phy = (void __iomem *)SCFG_USB_PHY2;
 206         PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
 207
 208         usb_phy = (void __iomem *)SCFG_USB_PHY3;
 209         PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
 210 #endif
 211 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
 212         defined(CONFIG_ARCH_LS1028A)
 213         void __iomem *dcsr = (void __iomem *)DCSR_BASE;
 214
 215         PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
 216         PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
 217 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
 218 }
 219
 220 #if defined(CONFIG_FSL_LSCH3)
 221 static void erratum_a050204(void)
 222 {
 223 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 224         void __iomem *dcsr = (void __iomem *)DCSR_BASE;
 225
 226         PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
 227         PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
 228 #endif
 229 }
 230 /*
 231  * This erratum requires setting a value to eddrtqcr1 to
 232  * optimal the DDR performance.
 233  */
 234 static void erratum_a008336(void)
 235 {
 236 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
 237         u32 *eddrtqcr1;
 238
 239 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
 240         eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
 241         if (fsl_ddr_get_version(0) == 0x50200)
 242                 out_le32(eddrtqcr1, 0x63b30002);
 243 #endif
 244 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
 245         eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
 246         if (fsl_ddr_get_version(0) == 0x50200)
 247                 out_le32(eddrtqcr1, 0x63b30002);
 248 #endif
 249 #endif
 250 }
 251
 252 /*
 253  * This erratum requires a register write before being Memory
 254  * controller 3 being enabled.
 255  */
 256 static void erratum_a008514(void)
 257 {
 258 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
 259         u32 *eddrtqcr1;
 260
 261 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
 262         eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
 263         out_le32(eddrtqcr1, 0x63b20002);
 264 #endif
 265 #endif
 266 }
 267 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 268 #define PLATFORM_CYCLE_ENV_VAR  "a009635_interval_val"
 269
 270 static unsigned long get_internval_val_mhz(void)
 271 {
 272         char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
 273         /*
 274          *  interval is the number of platform cycles(MHz) between
 275          *  wake up events generated by EPU.
 276          */
 277         ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
 278
 279         if (interval)
 280                 interval_mhz = simple_strtoul(interval, NULL, 10);
 281
 282         return interval_mhz;
 283 }
 284
 285 void erratum_a009635(void)
 286 {
 287         u32 val;
 288         unsigned long interval_mhz = get_internval_val_mhz();
 289
 290         if (!interval_mhz)
 291                 return;
 292
 293         val = in_le32(DCSR_CGACRE5);
 294         writel(val | 0x00000200, DCSR_CGACRE5);
 295
 296         val = in_le32(EPU_EPCMPR5);
 297         writel(interval_mhz, EPU_EPCMPR5);
 298         val = in_le32(EPU_EPCCR5);
 299         writel(val | 0x82820000, EPU_EPCCR5);
 300         val = in_le32(EPU_EPSMCR5);
 301         writel(val | 0x002f0000, EPU_EPSMCR5);
 302         val = in_le32(EPU_EPECR5);
 303         writel(val | 0x20000000, EPU_EPECR5);
 304         val = in_le32(EPU_EPGCR);
 305         writel(val | 0x80000000, EPU_EPGCR);
 306 }
 307 #endif  /* CONFIG_SYS_FSL_ERRATUM_A009635 */
 308
 309 static void erratum_rcw_src(void)
 310 {
 311 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
 312         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 313         u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
 314         u32 val;
 315
 316         val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 317         val &= ~DCFG_PORSR1_RCW_SRC;
 318         val |= DCFG_PORSR1_RCW_SRC_NOR;
 319         out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
 320 #endif
 321 }
 322
 323 #define I2C_DEBUG_REG 0x6
 324 #define I2C_GLITCH_EN 0x8
 325 /*
 326  * This erratum requires setting glitch_en bit to enable
 327  * digital glitch filter to improve clock stability.
 328  */
 329 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
 330 static void erratum_a009203(void)
 331 {
 332 #ifdef CONFIG_SYS_I2C
 333         u8 __iomem *ptr;
 334 #ifdef I2C1_BASE_ADDR
 335         ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
 336
 337         writeb(I2C_GLITCH_EN, ptr);
 338 #endif
 339 #ifdef I2C2_BASE_ADDR
 340         ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
 341
 342         writeb(I2C_GLITCH_EN, ptr);
 343 #endif
 344 #ifdef I2C3_BASE_ADDR
 345         ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
 346
 347         writeb(I2C_GLITCH_EN, ptr);
 348 #endif
 349 #ifdef I2C4_BASE_ADDR
 350         ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
 351
 352         writeb(I2C_GLITCH_EN, ptr);
 353 #endif
 354 #endif
 355 }
 356 #endif
 357
 358 void bypass_smmu(void)
 359 {
 360         u32 val;
 361         val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 362         out_le32(SMMU_SCR0, val);
 363         val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 364         out_le32(SMMU_NSCR0, val);
 365 }
 366 void fsl_lsch3_early_init_f(void)
 367 {
 368         erratum_rcw_src();
 369 #ifdef CONFIG_FSL_IFC
 370         init_early_memctl_regs();       /* tighten IFC timing */
 371 #endif
 372 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
 373         erratum_a009203();
 374 #endif
 375         erratum_a008514();
 376         erratum_a008336();
 377         erratum_a009008();
 378         erratum_a009798();
 379         erratum_a008997();
 380         erratum_a009007();
 381         erratum_a050204();
 382 #ifdef CONFIG_CHAIN_OF_TRUST
 383         /* In case of Secure Boot, the IBR configures the SMMU
 384         * to allow only Secure transactions.
 385         * SMMU must be reset in bypass mode.
 386         * Set the ClientPD bit and Clear the USFCFG Bit
 387         */
 388         if (fsl_check_boot_mode_secure() == 1)
 389                 bypass_smmu();
 390 #endif
 391
 392 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
 393         defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
 394         defined(CONFIG_ARCH_LX2162A)
 395         set_icids();
 396 #endif
 397 }
 398
 399 /* Get VDD in the unit mV from voltage ID */
 400 int get_core_volt_from_fuse(void)
 401 {
 402         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 403         int vdd;
 404         u32 fusesr;
 405         u8 vid;
 406
 407         /* get the voltage ID from fuse status register */
 408         fusesr = in_le32(&gur->dcfg_fusesr);
 409         debug("%s: fusesr = 0x%x\n", __func__, fusesr);
 410         vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
 411                 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
 412         if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
 413                 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
 414                         FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
 415         }
 416         debug("%s: VID = 0x%x\n", __func__, vid);
 417         switch (vid) {
 418         case 0x00: /* VID isn't supported */
 419                 vdd = -EINVAL;
 420                 debug("%s: The VID feature is not supported\n", __func__);
 421                 break;
 422         case 0x08: /* 0.9V silicon */
 423                 vdd = 900;
 424                 break;
 425         case 0x10: /* 1.0V silicon */
 426                 vdd = 1000;
 427                 break;
 428         default:  /* Other core voltage */
 429                 vdd = -EINVAL;
 430                 debug("%s: The VID(%x) isn't supported\n", __func__, vid);
 431                 break;
 432         }
 433         debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
 434
 435         return vdd;
 436 }
 437
 438 #elif defined(CONFIG_FSL_LSCH2)
 439 /*
 440  * This erratum requires setting a value to eddrtqcr1 to optimal
 441  * the DDR performance. The eddrtqcr1 register is in SCFG space
 442  * of LS1043A and the offset is 0x157_020c.
 443  */
 444 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
 445         && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
 446 #error A009660 and A008514 can not be both enabled.
 447 #endif
 448
 449 static void erratum_a009660(void)
 450 {
 451 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
 452         u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
 453         out_be32(eddrtqcr1, 0x63b20042);
 454 #endif
 455 }
 456
 457 static void erratum_a008850_early(void)
 458 {
 459 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
 460         /* part 1 of 2 */
 461         struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
 462                                                 CONFIG_SYS_CCI400_OFFSET);
 463         struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 464
 465         /* Skip if running at lower exception level */
 466         if (current_el() < 3)
 467                 return;
 468
 469         /* disables propagation of barrier transactions to DDRC from CCI400 */
 470         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 471
 472         /* disable the re-ordering in DDRC */
 473         ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
 474 #endif
 475 }
 476
 477 void erratum_a008850_post(void)
 478 {
 479 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
 480         /* part 2 of 2 */
 481         struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
 482                                                 CONFIG_SYS_CCI400_OFFSET);
 483         struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 484         u32 tmp;
 485
 486         /* Skip if running at lower exception level */
 487         if (current_el() < 3)
 488                 return;
 489
 490         /* enable propagation of barrier transactions to DDRC from CCI400 */
 491         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 492
 493         /* enable the re-ordering in DDRC */
 494         tmp = ddr_in32(&ddr->eor);
 495         tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
 496         ddr_out32(&ddr->eor, tmp);
 497 #endif
 498 }
 499
 500 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 501 void erratum_a010315(void)
 502 {
 503         int i;
 504
 505         for (i = PCIE1; i <= PCIE4; i++)
 506                 if (!is_serdes_configured(i)) {
 507                         debug("PCIe%d: disabled all R/W permission!\n", i);
 508                         set_pcie_ns_access(i, 0);
 509                 }
 510 }
 511 #endif
 512
 513 static void erratum_a010539(void)
 514 {
 515 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
 516         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 517         u32 porsr1;
 518
 519         porsr1 = in_be32(&gur->porsr1);
 520         porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
 521         out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 522                  porsr1);
 523         out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
 524 #endif
 525 }
 526
 527 /* Get VDD in the unit mV from voltage ID */
 528 int get_core_volt_from_fuse(void)
 529 {
 530         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 531         int vdd;
 532         u32 fusesr;
 533         u8 vid;
 534
 535         fusesr = in_be32(&gur->dcfg_fusesr);
 536         debug("%s: fusesr = 0x%x\n", __func__, fusesr);
 537         vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
 538                 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
 539         if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
 540                 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
 541                         FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
 542         }
 543         debug("%s: VID = 0x%x\n", __func__, vid);
 544         switch (vid) {
 545         case 0x00: /* VID isn't supported */
 546                 vdd = -EINVAL;
 547                 debug("%s: The VID feature is not supported\n", __func__);
 548                 break;
 549         case 0x08: /* 0.9V silicon */
 550                 vdd = 900;
 551                 break;
 552         case 0x10: /* 1.0V silicon */
 553                 vdd = 1000;
 554                 break;
 555         default:  /* Other core voltage */
 556                 vdd = -EINVAL;
 557                 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
 558                 break;
 559         }
 560         debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
 561
 562         return vdd;
 563 }
 564
 565 __weak int board_switch_core_volt(u32 vdd)
 566 {
 567         return 0;
 568 }
 569
 570 static int setup_core_volt(u32 vdd)
 571 {
 572         return board_setup_core_volt(vdd);
 573 }
 574
 575 #ifdef CONFIG_SYS_FSL_DDR
 576 static void ddr_enable_0v9_volt(bool en)
 577 {
 578         struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 579         u32 tmp;
 580
 581         tmp = ddr_in32(&ddr->ddr_cdr1);
 582
 583         if (en)
 584                 tmp |= DDR_CDR1_V0PT9_EN;
 585         else
 586                 tmp &= ~DDR_CDR1_V0PT9_EN;
 587
 588         ddr_out32(&ddr->ddr_cdr1, tmp);
 589 }
 590 #endif
 591
 592 int setup_chip_volt(void)
 593 {
 594         int vdd;
 595
 596         vdd = get_core_volt_from_fuse();
 597         /* Nothing to do for silicons doesn't support VID */
 598         if (vdd < 0)
 599                 return vdd;
 600
 601         if (setup_core_volt(vdd))
 602                 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
 603 #ifdef CONFIG_SYS_HAS_SERDES
 604         if (setup_serdes_volt(vdd))
 605                 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
 606 #endif
 607
 608 #ifdef CONFIG_SYS_FSL_DDR
 609         if (vdd == 900)
 610                 ddr_enable_0v9_volt(true);
 611 #endif
 612
 613         return 0;
 614 }
 615
 616 #ifdef CONFIG_FSL_PFE
 617 void init_pfe_scfg_dcfg_regs(void)
 618 {
 619         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 620         u32 ecccr2;
 621
 622         out_be32(&scfg->pfeasbcr,
 623                  in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
 624         out_be32(&scfg->pfebsbcr,
 625                  in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
 626
 627         /* CCI-400 QoS settings for PFE */
 628         out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
 629                  | SCFG_WR_QOS1_PFE2_QOS));
 630         out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
 631                  | SCFG_RD_QOS1_PFE2_QOS));
 632
 633         ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
 634         out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
 635                  ecccr2 | (unsigned int)DISABLE_PFE_ECC);
 636 }
 637 #endif
 638
 639 void fsl_lsch2_early_init_f(void)
 640 {
 641         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 642                                         CONFIG_SYS_CCI400_OFFSET);
 643         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 644 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
 645         enum boot_src src;
 646 #endif
 647
 648 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 649         enable_layerscape_ns_access();
 650 #endif
 651
 652 #ifdef CONFIG_FSL_IFC
 653         init_early_memctl_regs();       /* tighten IFC timing */
 654 #endif
 655
 656 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
 657         src = get_boot_src();
 658         if (src != BOOT_SOURCE_QSPI_NOR)
 659                 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 660 #else
 661 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
 662         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 663 #endif
 664 #endif
 665         /* Make SEC reads and writes snoopable */
 666 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 667         setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
 668                         SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
 669                         SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
 670                         SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
 671                         SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
 672                         SCFG_SNPCNFGCR_SATAWRSNP);
 673 #elif defined(CONFIG_ARCH_LS1012A)
 674         setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
 675                         SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
 676                         SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
 677                         SCFG_SNPCNFGCR_SATAWRSNP);
 678 #else
 679         setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
 680                      SCFG_SNPCNFGCR_SECWRSNP |
 681                      SCFG_SNPCNFGCR_SATARDSNP |
 682                      SCFG_SNPCNFGCR_SATAWRSNP);
 683 #endif
 684
 685         /*
 686          * Enable snoop requests and DVM message requests for
 687          * Slave insterface S4 (A53 core cluster)
 688          */
 689         if (current_el() == 3) {
 690                 out_le32(&cci->slave[4].snoop_ctrl,
 691                          CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 692         }
 693
 694         /*
 695          * Program Central Security Unit (CSU) to grant access
 696          * permission for USB 2.0 controller
 697          */
 698 #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
 699         if (current_el() == 3)
 700                 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
 701 #endif
 702         /* Erratum */
 703         erratum_a008850_early(); /* part 1 of 2 */
 704         erratum_a009660();
 705         erratum_a010539();
 706         erratum_a009008();
 707         erratum_a009798();
 708         erratum_a008997();
 709         erratum_a009007();
 710
 711 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 712         set_icids();
 713 #endif
 714 }
 715 #endif
 716
 717 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
 718 int fspi_ahb_init(void)
 719 {
 720         /* Enable 4bytes address support and fast read */
 721         u32 *fspi_lut, lut_key, *fspi_key;
 722
 723         fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
 724         fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
 725
 726         lut_key = in_be32(fspi_key);
 727
 728         if (lut_key == SYS_NXP_FSPI_LUTKEY) {
 729                 /* That means the register is BE */
 730                 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
 731                 /* Unlock the lut table */
 732                 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
 733                 /* Create READ LUT */
 734                 out_be32(fspi_lut, 0x0820040c);
 735                 out_be32(fspi_lut + 1, 0x24003008);
 736                 out_be32(fspi_lut + 2, 0x00000000);
 737                 /* Lock the lut table */
 738                 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
 739                 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
 740         } else {
 741                 /* That means the register is LE */
 742                 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
 743                 /* Unlock the lut table */
 744                 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
 745                 /* Create READ LUT */
 746                 out_le32(fspi_lut, 0x0820040c);
 747                 out_le32(fspi_lut + 1, 0x24003008);
 748                 out_le32(fspi_lut + 2, 0x00000000);
 749                 /* Lock the lut table */
 750                 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
 751                 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
 752         }
 753
 754         return 0;
 755 }
 756 #endif
 757
 758 #ifdef CONFIG_QSPI_AHB_INIT
 759 /* Enable 4bytes address support and fast read */
 760 int qspi_ahb_init(void)
 761 {
 762         u32 *qspi_lut, lut_key, *qspi_key;
 763
 764         qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
 765         qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
 766
 767         lut_key = in_be32(qspi_key);
 768
 769         if (lut_key == 0x5af05af0) {
 770                 /* That means the register is BE */
 771                 out_be32(qspi_key, 0x5af05af0);
 772                 /* Unlock the lut table */
 773                 out_be32(qspi_key + 1, 0x00000002);
 774                 out_be32(qspi_lut, 0x0820040c);
 775                 out_be32(qspi_lut + 1, 0x1c080c08);
 776                 out_be32(qspi_lut + 2, 0x00002400);
 777                 /* Lock the lut table */
 778                 out_be32(qspi_key, 0x5af05af0);
 779                 out_be32(qspi_key + 1, 0x00000001);
 780         } else {
 781                 /* That means the register is LE */
 782                 out_le32(qspi_key, 0x5af05af0);
 783                 /* Unlock the lut table */
 784                 out_le32(qspi_key + 1, 0x00000002);
 785                 out_le32(qspi_lut, 0x0820040c);
 786                 out_le32(qspi_lut + 1, 0x1c080c08);
 787                 out_le32(qspi_lut + 2, 0x00002400);
 788                 /* Lock the lut table */
 789                 out_le32(qspi_key, 0x5af05af0);
 790                 out_le32(qspi_key + 1, 0x00000001);
 791         }
 792
 793         return 0;
 794 }
 795 #endif
 796
 797 #ifdef CONFIG_TFABOOT
 798 #define MAX_BOOTCMD_SIZE        512
 799
 800 int fsl_setenv_bootcmd(void)
 801 {
 802         int ret;
 803         enum boot_src src = get_boot_src();
 804         char bootcmd_str[MAX_BOOTCMD_SIZE];
 805
 806         switch (src) {
 807 #ifdef IFC_NOR_BOOTCOMMAND
 808         case BOOT_SOURCE_IFC_NOR:
 809                 sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
 810                 break;
 811 #endif
 812 #ifdef QSPI_NOR_BOOTCOMMAND
 813         case BOOT_SOURCE_QSPI_NOR:
 814                 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
 815                 break;
 816 #endif
 817 #ifdef XSPI_NOR_BOOTCOMMAND
 818         case BOOT_SOURCE_XSPI_NOR:
 819                 sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
 820                 break;
 821 #endif
 822 #ifdef IFC_NAND_BOOTCOMMAND
 823         case BOOT_SOURCE_IFC_NAND:
 824                 sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
 825                 break;
 826 #endif
 827 #ifdef QSPI_NAND_BOOTCOMMAND
 828         case BOOT_SOURCE_QSPI_NAND:
 829                 sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
 830                 break;
 831 #endif
 832 #ifdef XSPI_NAND_BOOTCOMMAND
 833         case BOOT_SOURCE_XSPI_NAND:
 834                 sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
 835                 break;
 836 #endif
 837 #ifdef SD_BOOTCOMMAND
 838         case BOOT_SOURCE_SD_MMC:
 839                 sprintf(bootcmd_str, SD_BOOTCOMMAND);
 840                 break;
 841 #endif
 842 #ifdef SD2_BOOTCOMMAND
 843         case BOOT_SOURCE_SD_MMC2:
 844                 sprintf(bootcmd_str, SD2_BOOTCOMMAND);
 845                 break;
 846 #endif
 847         default:
 848 #ifdef QSPI_NOR_BOOTCOMMAND
 849                 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
 850 #endif
 851                 break;
 852         }
 853
 854         ret = env_set("bootcmd", bootcmd_str);
 855         if (ret) {
 856                 printf("Failed to set bootcmd: ret = %d\n", ret);
 857                 return ret;
 858         }
 859         return 0;
 860 }
 861
 862 int fsl_setenv_mcinitcmd(void)
 863 {
 864         int ret = 0;
 865         enum boot_src src = get_boot_src();
 866
 867         switch (src) {
 868 #ifdef IFC_MC_INIT_CMD
 869         case BOOT_SOURCE_IFC_NAND:
 870         case BOOT_SOURCE_IFC_NOR:
 871         ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
 872                 break;
 873 #endif
 874 #ifdef QSPI_MC_INIT_CMD
 875         case BOOT_SOURCE_QSPI_NAND:
 876         case BOOT_SOURCE_QSPI_NOR:
 877         ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
 878                 break;
 879 #endif
 880 #ifdef XSPI_MC_INIT_CMD
 881         case BOOT_SOURCE_XSPI_NAND:
 882         case BOOT_SOURCE_XSPI_NOR:
 883         ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
 884                 break;
 885 #endif
 886 #ifdef SD_MC_INIT_CMD
 887         case BOOT_SOURCE_SD_MMC:
 888         ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
 889                 break;
 890 #endif
 891 #ifdef SD2_MC_INIT_CMD
 892         case BOOT_SOURCE_SD_MMC2:
 893         ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
 894                 break;
 895 #endif
 896         default:
 897 #ifdef QSPI_MC_INIT_CMD
 898         ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
 899 #endif
 900                 break;
 901         }
 902
 903         if (ret) {
 904                 printf("Failed to set mcinitcmd: ret = %d\n", ret);
 905                 return ret;
 906         }
 907         return 0;
 908 }
 909 #endif
 910
 911 #ifdef CONFIG_BOARD_LATE_INIT
 912 __weak int fsl_board_late_init(void)
 913 {
 914         return 0;
 915 }
 916
 917 #define DWC3_GSBUSCFG0                  0xc100
 918 #define DWC3_GSBUSCFG0_CACHETYPE_SHIFT  16
 919 #define DWC3_GSBUSCFG0_CACHETYPE(n)        (((n) & 0xffff)            \
 920         << DWC3_GSBUSCFG0_CACHETYPE_SHIFT)
 921
 922 void enable_dwc3_snooping(void)
 923 {
 924         int ret;
 925         u32 val;
 926         struct udevice *bus;
 927         struct uclass *uc;
 928         fdt_addr_t dwc3_base;
 929
 930         ret = uclass_get(UCLASS_USB, &uc);
 931         if (ret)
 932                 return;
 933
 934         uclass_foreach_dev(bus, uc) {
 935                 if (!strcmp(bus->driver->of_match->compatible, "fsl,layerscape-dwc3")) {
 936                         dwc3_base = devfdt_get_addr(bus);
 937                         if (dwc3_base == FDT_ADDR_T_NONE) {
 938                                 dev_err(bus, "dwc3 regs missing\n");
 939                                 continue;
 940                         }
 941                         val = in_le32(dwc3_base + DWC3_GSBUSCFG0);
 942                         val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0);
 943                         val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222);
 944                         writel(val, dwc3_base + DWC3_GSBUSCFG0);
 945                 }
 946         }
 947 }
 948
 949 int board_late_init(void)
 950 {
 951 #ifdef CONFIG_CHAIN_OF_TRUST
 952         fsl_setenv_chain_of_trust();
 953 #endif
 954 #ifdef CONFIG_TFABOOT
 955         /*
 956          * Set bootcmd and mcinitcmd if they don't exist in the environment.
 957          */
 958         if (!env_get("bootcmd"))
 959                 fsl_setenv_bootcmd();
 960         if (!env_get("mcinitcmd"))
 961                 fsl_setenv_mcinitcmd();
 962 #endif
 963 #ifdef CONFIG_QSPI_AHB_INIT
 964         qspi_ahb_init();
 965 #endif
 966 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
 967         fspi_ahb_init();
 968 #endif
 969
 970         if (IS_ENABLED(CONFIG_DM))
 971                 enable_dwc3_snooping();
 972
 973         return fsl_board_late_init();
 974 }
 975 #endif