2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fsl_serdes.h>
11 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
12 #include <fsl-mc/ldpaa_wriop.h>
14 #ifdef CONFIG_SYS_FSL_SRDS_1
15 static u8 serdes1_prtcl_map
[SERDES_PRCTL_COUNT
];
17 #ifdef CONFIG_SYS_FSL_SRDS_2
18 static u8 serdes2_prtcl_map
[SERDES_PRCTL_COUNT
];
21 int is_serdes_configured(enum srds_prtcl device
)
25 #ifdef CONFIG_SYS_FSL_SRDS_1
26 ret
|= serdes1_prtcl_map
[device
];
28 #ifdef CONFIG_SYS_FSL_SRDS_2
29 ret
|= serdes2_prtcl_map
[device
];
35 int serdes_get_first_lane(u32 sd
, enum srds_prtcl device
)
37 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
38 u32 cfg
= in_le32(&gur
->rcwsr
[28]);
42 #ifdef CONFIG_SYS_FSL_SRDS_1
44 cfg
&= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
;
45 cfg
>>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
;
48 #ifdef CONFIG_SYS_FSL_SRDS_2
50 cfg
&= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
;
51 cfg
>>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
;
55 printf("invalid SerDes%d\n", sd
);
58 /* Is serdes enabled at all? */
62 for (i
= 0; i
< SRDS_MAX_LANES
; i
++) {
63 if (serdes_get_prtcl(sd
, cfg
, i
) == device
)
70 void serdes_init(u32 sd
, u32 sd_addr
, u32 sd_prctl_mask
, u32 sd_prctl_shift
,
71 u8 serdes_prtcl_map
[SERDES_PRCTL_COUNT
])
73 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
77 memset(serdes_prtcl_map
, 0, sizeof(serdes_prtcl_map
));
79 cfg
= in_le32(&gur
->rcwsr
[28]) & sd_prctl_mask
;
80 cfg
>>= sd_prctl_shift
;
81 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd
+ 1, cfg
, cfg
);
83 if (!is_serdes_prtcl_valid(sd
, cfg
))
84 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd
+ 1, cfg
);
86 for (lane
= 0; lane
< SRDS_MAX_LANES
; lane
++) {
87 enum srds_prtcl lane_prtcl
= serdes_get_prtcl(sd
, cfg
, lane
);
88 if (unlikely(lane_prtcl
>= SERDES_PRCTL_COUNT
))
89 debug("Unknown SerDes lane protocol %d\n", lane_prtcl
);
91 serdes_prtcl_map
[lane_prtcl
] = 1;
92 #ifdef CONFIG_FSL_MC_ENET
95 wriop_init_dpmac(sd
, 5, (int)lane_prtcl
);
96 wriop_init_dpmac(sd
, 6, (int)lane_prtcl
);
97 wriop_init_dpmac(sd
, 7, (int)lane_prtcl
);
98 wriop_init_dpmac(sd
, 8, (int)lane_prtcl
);
101 wriop_init_dpmac(sd
, 1, (int)lane_prtcl
);
102 wriop_init_dpmac(sd
, 2, (int)lane_prtcl
);
103 wriop_init_dpmac(sd
, 3, (int)lane_prtcl
);
104 wriop_init_dpmac(sd
, 4, (int)lane_prtcl
);
107 wriop_init_dpmac(sd
, 13, (int)lane_prtcl
);
108 wriop_init_dpmac(sd
, 14, (int)lane_prtcl
);
109 wriop_init_dpmac(sd
, 15, (int)lane_prtcl
);
110 wriop_init_dpmac(sd
, 16, (int)lane_prtcl
);
113 wriop_init_dpmac(sd
, 9, (int)lane_prtcl
);
114 wriop_init_dpmac(sd
, 10, (int)lane_prtcl
);
115 wriop_init_dpmac(sd
, 11, (int)lane_prtcl
);
116 wriop_init_dpmac(sd
, 12, (int)lane_prtcl
);
119 if (lane_prtcl
>= SGMII1
&&
120 lane_prtcl
<= SGMII16
)
121 wriop_init_dpmac(sd
, lane
+ 1,
130 void fsl_serdes_init(void)
132 #ifdef CONFIG_SYS_FSL_SRDS_1
133 serdes_init(FSL_SRDS_1
,
134 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
,
135 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
,
136 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
,
139 #ifdef CONFIG_SYS_FSL_SRDS_2
140 serdes_init(FSL_SRDS_2
,
141 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
+ FSL_SRDS_2
* 0x10000,
142 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
,
143 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
,