1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
8 #include <asm/arch/hardware.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/armv8/mmu.h>
13 #define ZYNQ_SILICON_VER_MASK 0xF000
14 #define ZYNQ_SILICON_VER_SHIFT 12
16 DECLARE_GLOBAL_DATA_PTR
;
19 * Number of filled static entries and also the first empty
20 * slot in zynqmp_mem_map.
22 #define ZYNQMP_MEM_MAP_USED 4
24 #if !defined(CONFIG_ZYNQMP_NO_DDR)
25 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
30 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
36 /* +1 is end of list which needs to be empty */
37 #define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
39 static struct mm_region zynqmp_mem_map
[ZYNQMP_MEM_MAP_MAX
] = {
44 .attrs
= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE
) |
46 PTE_BLOCK_PXN
| PTE_BLOCK_UXN
51 .attrs
= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE
) |
53 PTE_BLOCK_PXN
| PTE_BLOCK_UXN
55 .virt
= 0x400000000UL
,
56 .phys
= 0x400000000UL
,
57 .size
= 0x400000000UL
,
58 .attrs
= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE
) |
60 PTE_BLOCK_PXN
| PTE_BLOCK_UXN
62 .virt
= 0x1000000000UL
,
63 .phys
= 0x1000000000UL
,
64 .size
= 0xf000000000UL
,
65 .attrs
= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE
) |
67 PTE_BLOCK_PXN
| PTE_BLOCK_UXN
71 void mem_map_fill(void)
73 int banks
= ZYNQMP_MEM_MAP_USED
;
75 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
76 zynqmp_mem_map
[banks
].virt
= 0xffe00000UL
;
77 zynqmp_mem_map
[banks
].phys
= 0xffe00000UL
;
78 zynqmp_mem_map
[banks
].size
= 0x00200000UL
;
79 zynqmp_mem_map
[banks
].attrs
= PTE_BLOCK_MEMTYPE(MT_NORMAL
) |
80 PTE_BLOCK_INNER_SHARE
;
84 #if !defined(CONFIG_ZYNQMP_NO_DDR)
85 for (int i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++) {
86 /* Zero size means no more DDR that's this is end */
87 if (!gd
->bd
->bi_dram
[i
].size
)
90 zynqmp_mem_map
[banks
].virt
= gd
->bd
->bi_dram
[i
].start
;
91 zynqmp_mem_map
[banks
].phys
= gd
->bd
->bi_dram
[i
].start
;
92 zynqmp_mem_map
[banks
].size
= gd
->bd
->bi_dram
[i
].size
;
93 zynqmp_mem_map
[banks
].attrs
= PTE_BLOCK_MEMTYPE(MT_NORMAL
) |
94 PTE_BLOCK_INNER_SHARE
;
100 struct mm_region
*mem_map
= zynqmp_mem_map
;
102 u64
get_page_table_size(void)
107 #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
108 int reserve_mmu(void)
110 initialize_tcm(TCM_LOCK
);
111 memset((void *)ZYNQMP_TCM_BASE_ADDR
, 0, ZYNQMP_TCM_SIZE
);
112 gd
->arch
.tlb_size
= PGTABLE_SIZE
;
113 gd
->arch
.tlb_addr
= ZYNQMP_TCM_BASE_ADDR
;
119 static unsigned int zynqmp_get_silicon_version_secure(void)
123 ver
= readl(&csu_base
->version
);
124 ver
&= ZYNQMP_SILICON_VER_MASK
;
125 ver
>>= ZYNQMP_SILICON_VER_SHIFT
;
130 unsigned int zynqmp_get_silicon_version(void)
132 if (current_el() == 3)
133 return zynqmp_get_silicon_version_secure();
135 gd
->cpu_clk
= get_tbclk();
137 switch (gd
->cpu_clk
) {
139 return ZYNQMP_CSU_VERSION_QEMU
;
142 return ZYNQMP_CSU_VERSION_SILICON
;
145 #define ZYNQMP_MMIO_READ 0xC2000014
146 #define ZYNQMP_MMIO_WRITE 0xC2000013
148 int __maybe_unused
invoke_smc(u32 pm_api_id
, u32 arg0
, u32 arg1
, u32 arg2
,
149 u32 arg3
, u32
*ret_payload
)
152 * Added SIP service call Function Identifier
153 * Make sure to stay in x0 register
157 regs
.regs
[0] = pm_api_id
;
158 regs
.regs
[1] = ((u64
)arg1
<< 32) | arg0
;
159 regs
.regs
[2] = ((u64
)arg3
<< 32) | arg2
;
163 if (ret_payload
!= NULL
) {
164 ret_payload
[0] = (u32
)regs
.regs
[0];
165 ret_payload
[1] = upper_32_bits(regs
.regs
[0]);
166 ret_payload
[2] = (u32
)regs
.regs
[1];
167 ret_payload
[3] = upper_32_bits(regs
.regs
[1]);
168 ret_payload
[4] = (u32
)regs
.regs
[2];
174 #if defined(CONFIG_CLK_ZYNQMP)
175 void zynqmp_pmufw_version(void)
178 u32 ret_payload
[PAYLOAD_ARG_CNT
];
181 ret
= invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION
, 0, 0, 0, 0,
183 pm_api_version
= ret_payload
[1];
186 panic("PMUFW is not found - Please load it!\n");
188 printf("PMUFW:\tv%d.%d\n",
189 pm_api_version
>> ZYNQMP_PM_VERSION_MAJOR_SHIFT
,
190 pm_api_version
& ZYNQMP_PM_VERSION_MINOR_MASK
);
192 if (pm_api_version
< ZYNQMP_PM_VERSION
)
193 panic("PMUFW version error. Expected: v%d.%d\n",
194 ZYNQMP_PM_VERSION_MAJOR
, ZYNQMP_PM_VERSION_MINOR
);
198 static int zynqmp_mmio_rawwrite(const u32 address
,
203 u32 value_local
= value
;
206 ret
= zynqmp_mmio_read(address
, &data
);
213 writel(value_local
, (ulong
)address
);
217 static int zynqmp_mmio_rawread(const u32 address
, u32
*value
)
219 *value
= readl((ulong
)address
);
223 int zynqmp_mmio_write(const u32 address
,
227 if (IS_ENABLED(CONFIG_SPL_BUILD
) || current_el() == 3)
228 return zynqmp_mmio_rawwrite(address
, mask
, value
);
230 return invoke_smc(ZYNQMP_MMIO_WRITE
, address
, mask
,
236 int zynqmp_mmio_read(const u32 address
, u32
*value
)
238 u32 ret_payload
[PAYLOAD_ARG_CNT
];
244 if (IS_ENABLED(CONFIG_SPL_BUILD
) || current_el() == 3) {
245 ret
= zynqmp_mmio_rawread(address
, value
);
247 ret
= invoke_smc(ZYNQMP_MMIO_READ
, address
, 0, 0,
249 *value
= ret_payload
[1];