2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/hardware.h>
10 #include <asm/arch/sys_proto.h>
13 #define ZYNQ_SILICON_VER_MASK 0xF000
14 #define ZYNQ_SILICON_VER_SHIFT 12
16 DECLARE_GLOBAL_DATA_PTR
;
18 unsigned int zynqmp_get_silicon_version(void)
20 gd
->cpu_clk
= get_tbclk();
22 switch (gd
->cpu_clk
) {
24 return ZYNQMP_CSU_VERSION_VELOCE
;
26 return ZYNQMP_CSU_VERSION_QEMU
;
29 return ZYNQMP_CSU_VERSION_EP108
;
32 #ifndef CONFIG_SYS_DCACHE_OFF
33 #include <asm/armv8/mmu.h>
35 #define SECTION_SHIFT_L1 30UL
36 #define SECTION_SHIFT_L2 21UL
37 #define BLOCK_SIZE_L0 0x8000000000UL
38 #define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1)
39 #define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2)
41 #define TCR_TG1_4K (1 << 31)
42 #define TCR_EPD1_DISABLE (1 << 23)
43 #define ZYNQMO_VA_BITS 40
44 #define ZYNQMP_TCR TCR_TG1_4K | \
50 TCR_T0SZ(ZYNQMO_VA_BITS)
52 #define MEMORY_ATTR PMD_SECT_AF | PMD_SECT_INNER_SHARE | \
53 PMD_ATTRINDX(MT_NORMAL) | \
55 #define DEVICE_ATTR PMD_SECT_AF | PMD_SECT_PXN | \
56 PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \
59 /* 4K size is required to place 512 entries in each level */
60 #define TLB_TABLE_SIZE 0x1000
67 static struct attr_tbl attr_tbll1t0
[4] = { {16, 0x0},
72 static struct attr_tbl attr_tbll2t3
[4] = { {0x180, DEVICE_ATTR
},
79 * This mmu table looks as below
80 * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0
81 * and other Level1 Table1.
82 * Level1 Table0 contains entries for each 1GB from 0 to 511GB.
83 * Level1 Table1 contains entries for each 1GB from 512GB to 1TB.
84 * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains
85 * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively.
87 static void zynqmp_mmu_setup(void)
91 u64 i
, section_l1t0
, section_l1t1
;
92 u64 section_l2t0
, section_l2t1
, section_l2t2
, section_l2t3
;
93 u64
*level0_table
= (u64
*)gd
->arch
.tlb_addr
;
94 u64
*level1_table_0
= (u64
*)(gd
->arch
.tlb_addr
+ TLB_TABLE_SIZE
);
95 u64
*level1_table_1
= (u64
*)(gd
->arch
.tlb_addr
+ (2 * TLB_TABLE_SIZE
));
96 u64
*level2_table_0
= (u64
*)(gd
->arch
.tlb_addr
+ (3 * TLB_TABLE_SIZE
));
97 u64
*level2_table_1
= (u64
*)(gd
->arch
.tlb_addr
+ (4 * TLB_TABLE_SIZE
));
98 u64
*level2_table_2
= (u64
*)(gd
->arch
.tlb_addr
+ (5 * TLB_TABLE_SIZE
));
99 u64
*level2_table_3
= (u64
*)(gd
->arch
.tlb_addr
+ (6 * TLB_TABLE_SIZE
));
102 (u64
)level1_table_0
| PMD_TYPE_TABLE
;
104 (u64
)level1_table_1
| PMD_TYPE_TABLE
;
107 * set level 1 table 0, covering 0 to 512GB
108 * set level 1 table 1, covering 512GB to 1TB
111 section_l1t1
= BLOCK_SIZE_L0
;
114 for (i
= 0; i
< 512; i
++) {
115 level1_table_0
[i
] = section_l1t0
;
116 level1_table_0
[i
] |= attr_tbll1t0
[index_attr
].attr
;
117 attr_tbll1t0
[index_attr
].num
--;
118 if (attr_tbll1t0
[index_attr
].num
== 0)
120 level1_table_1
[i
] = section_l1t1
;
121 level1_table_1
[i
] |= DEVICE_ATTR
;
122 section_l1t0
+= BLOCK_SIZE_L1
;
123 section_l1t1
+= BLOCK_SIZE_L1
;
127 (u64
)level2_table_0
| PMD_TYPE_TABLE
;
129 (u64
)level2_table_1
| PMD_TYPE_TABLE
;
131 (u64
)level2_table_2
| PMD_TYPE_TABLE
;
133 (u64
)level2_table_3
| PMD_TYPE_TABLE
;
136 section_l2t1
= section_l2t0
+ BLOCK_SIZE_L1
; /* 1GB */
137 section_l2t2
= section_l2t1
+ BLOCK_SIZE_L1
; /* 2GB */
138 section_l2t3
= section_l2t2
+ BLOCK_SIZE_L1
; /* 3GB */
142 for (i
= 0; i
< 512; i
++) {
143 level2_table_0
[i
] = section_l2t0
| MEMORY_ATTR
;
144 level2_table_1
[i
] = section_l2t1
| MEMORY_ATTR
;
145 level2_table_2
[i
] = section_l2t2
| DEVICE_ATTR
;
146 level2_table_3
[i
] = section_l2t3
|
147 attr_tbll2t3
[index_attr
].attr
;
148 attr_tbll2t3
[index_attr
].num
--;
149 if (attr_tbll2t3
[index_attr
].num
== 0)
151 section_l2t0
+= BLOCK_SIZE_L2
;
152 section_l2t1
+= BLOCK_SIZE_L2
;
153 section_l2t2
+= BLOCK_SIZE_L2
;
154 section_l2t3
+= BLOCK_SIZE_L2
;
157 /* flush new MMU table */
158 flush_dcache_range(gd
->arch
.tlb_addr
,
159 gd
->arch
.tlb_addr
+ gd
->arch
.tlb_size
);
161 /* point TTBR to the new table */
163 set_ttbr_tcr_mair(el
, gd
->arch
.tlb_addr
,
164 ZYNQMP_TCR
, MEMORY_ATTRIBUTES
);
166 set_sctlr(get_sctlr() | CR_M
);
169 int arch_cpu_init(void)
172 __asm_invalidate_dcache_all();
173 __asm_invalidate_tlb_all();
178 * This function is called from lib/board.c.
179 * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
180 * There is no need to disable d-cache for this operation.
182 void enable_caches(void)
184 /* The data cache is not active unless the mmu is enabled */
185 if (!(get_sctlr() & CR_M
)) {
186 invalidate_dcache_all();
187 __asm_invalidate_tlb_all();
190 puts("Enabling Caches...\n");
192 set_sctlr(get_sctlr() | CR_C
);
195 u64
*arch_get_page_table(void)
197 return (u64
*)(gd
->arch
.tlb_addr
+ 0x3000);