arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h

   1 /**
   2  * @file IxEthAcc_p.h
   3  *
   4  * @author Intel Corporation
   5  * @date 12-Feb-2002
   6  *
   7  * @brief  Internal Header file for IXP425 Ethernet Access component.
   8  *
   9  * Design Notes:
  10  *
  11  *
  12  * @par
  13  * IXP400 SW Release version 2.0
  14  *
  15  * -- Copyright Notice --
  16  *
  17  * @par
  18  * Copyright 2001-2005, Intel Corporation.
  19  * All rights reserved.
  20  *
  21  * @par
  22  * Redistribution and use in source and binary forms, with or without
  23  * modification, are permitted provided that the following conditions
  24  * are met:
  25  * 1. Redistributions of source code must retain the above copyright
  26  *    notice, this list of conditions and the following disclaimer.
  27  * 2. Redistributions in binary form must reproduce the above copyright
  28  *    notice, this list of conditions and the following disclaimer in the
  29  *    documentation and/or other materials provided with the distribution.
  30  * 3. Neither the name of the Intel Corporation nor the names of its contributors
  31  *    may be used to endorse or promote products derived from this software
  32  *    without specific prior written permission.
  33  *
  34  * @par
  35  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
  36  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  37  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  38  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
  39  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  40  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  41  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  42  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  43  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  44  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  45  * SUCH DAMAGE.
  46  *
  47  * @par
  48  * -- End of Copyright Notice --
  49  */
  50
  51 /**
  52  * @addtogroup IxEthAccPri
  53  *@{
  54  */
  55
  56 #ifndef IxEthAcc_p_H
  57 #define IxEthAcc_p_H
  58
  59 /*
  60  * Os/System dependancies.
  61  */
  62 #include "IxOsal.h"
  63
  64 /*
  65  * Intermodule dependancies
  66  */
  67 #include "IxNpeDl.h"
  68 #include "IxQMgr.h"
  69
  70 #include "IxEthNpe.h"
  71
  72 /*
  73  * Intra module dependancies
  74  */
  75
  76 #include "IxEthAccDataPlane_p.h"
  77 #include "IxEthAccMac_p.h"
  78
  79
  80 #define INLINE __inline__
  81
  82 #ifdef NDEBUG
  83
  84 #define IX_ETH_ACC_PRIVATE static
  85
  86 #else
  87
  88 #define IX_ETH_ACC_PRIVATE
  89
  90 #endif /* ndef NDEBUG */
  91
  92 #define IX_ETH_ACC_PUBLIC
  93
  94
  95 #define IX_ETH_ACC_IS_PORT_VALID(port) ((port) <  IX_ETH_ACC_NUMBER_OF_PORTS  ? TRUE : FALSE )
  96
  97
  98
  99 #ifndef NDEBUG
 100 #define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g)   { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
 101 #define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
 102 #define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g)   { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
 103 #else
 104 #define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g)   { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
 105 #define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
 106 #define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g)   {}
 107 #endif
 108
 109 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccInitDataPlane(void);
 110 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrQueuesConfig(void);
 111 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback);
 112 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId);
 113 IX_ETH_ACC_PUBLIC void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries);
 114
 115 /* prototypes for the private control plane functions (used by the control interface wrapper) */
 116 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnablePriv(IxEthAccPortId portId);
 117 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDisablePriv(IxEthAccPortId portId);
 118 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled);
 119 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId);
 120 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId);
 121 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
 122 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressGetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
 123 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
 124 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinAllPriv(IxEthAccPortId portId);
 125 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeavePriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
 126 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeaveAllPriv(IxEthAccPortId portId);
 127 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShowPriv(IxEthAccPortId portId);
 128 IX_ETH_ACC_PUBLIC void ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId);
 129 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeSetPriv(IxEthAccPortId portId, IxEthAccDuplexMode mode);
 130 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeGetPriv(IxEthAccPortId portId, IxEthAccDuplexMode *mode);
 131 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingEnablePriv(IxEthAccPortId portId);
 132 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingDisablePriv(IxEthAccPortId portId);
 133 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
 134 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
 135 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
 136 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
 137 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched);
 138 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline sched);
 139
 140 /**
 141  * @struct  ixEthAccRxDataStats
 142  * @brief   Stats data structures for data path. - Not obtained from h/w
 143  *
 144  */
 145 typedef struct
 146 {
 147     UINT32 rxFrameClientCallback;
 148     UINT32 rxFreeRepOK;
 149     UINT32 rxFreeRepDelayed;
 150     UINT32 rxFreeRepFromSwQOK;
 151     UINT32 rxFreeRepFromSwQDelayed;
 152     UINT32 rxFreeLateNotificationEnabled;
 153     UINT32 rxFreeLowCallback;
 154     UINT32 rxFreeOverflow;
 155     UINT32 rxFreeLock;
 156     UINT32 rxDuringDisable;
 157     UINT32 rxSwQDuringDisable;
 158     UINT32 rxUnlearnedMacAddress;
 159     UINT32 rxPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
 160     UINT32 rxUnexpectedError;
 161     UINT32 rxFiltered;
 162 } IxEthAccRxDataStats;
 163
 164 /**
 165  * @struct  IxEthAccTxDataStats
 166  * @brief   Stats data structures for data path. - Not obtained from h/w
 167  *
 168  */
 169 typedef struct
 170 {
 171     UINT32 txQOK;
 172     UINT32 txQDelayed;
 173     UINT32 txFromSwQOK;
 174     UINT32 txFromSwQDelayed;
 175     UINT32 txLowThreshCallback;
 176     UINT32 txDoneClientCallback;
 177     UINT32 txDoneClientCallbackDisable;
 178     UINT32 txOverflow;
 179     UINT32 txLock;
 180     UINT32 txPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
 181     UINT32 txLateNotificationEnabled;
 182     UINT32 txDoneDuringDisable;
 183     UINT32 txDoneSwQDuringDisable;
 184     UINT32 txUnexpectedError;
 185 } IxEthAccTxDataStats;
 186
 187 /* port Disable state machine : list of states */
 188 typedef enum
 189 {
 190     /* general port states */
 191     DISABLED = 0,
 192     ACTIVE,
 193
 194     /* particular Tx/Rx states */
 195     REPLENISH,
 196     RECEIVE,
 197     TRANSMIT,
 198     TRANSMIT_DONE
 199 } IxEthAccPortDisableState;
 200
 201 typedef struct
 202 {
 203     BOOL fullDuplex;
 204     BOOL rxFCSAppend;
 205     BOOL txFCSAppend;
 206     BOOL txPADAppend;
 207     BOOL enabled;
 208     BOOL promiscuous;
 209     BOOL joinAll;
 210     IxOsalMutex ackMIBStatsLock;
 211     IxOsalMutex ackMIBStatsResetLock;
 212     IxOsalMutex MIBStatsGetAccessLock;
 213     IxOsalMutex MIBStatsGetResetAccessLock;
 214     IxOsalMutex npeLoopbackMessageLock;
 215     IxEthAccMacAddr mcastAddrsTable[IX_ETH_ACC_MAX_MULTICAST_ADDRESSES];
 216     UINT32 mcastAddrIndex;
 217     IX_OSAL_MBUF *portDisableTxMbufPtr;
 218     IX_OSAL_MBUF *portDisableRxMbufPtr;
 219
 220     volatile IxEthAccPortDisableState portDisableState;
 221     volatile IxEthAccPortDisableState rxState;
 222     volatile IxEthAccPortDisableState txState;
 223
 224     BOOL initDone;
 225     BOOL macInitialised;
 226 } IxEthAccMacState;
 227
 228 /**
 229  * @struct  IxEthAccRxInfo
 230  * @brief   System-wide data structures associated with the data plane.
 231  *
 232  */
 233 typedef struct
 234 {
 235   IxQMgrQId higherPriorityQueue[IX_QMGR_MAX_NUM_QUEUES]; /**< higher priority queue list */
 236   IxEthAccSchedulerDiscipline schDiscipline; /**< Receive Xscale QoS type */
 237 } IxEthAccInfo;
 238
 239 /**
 240  * @struct  IxEthAccRxDataInfo
 241  * @brief   Per Port data structures associated with the receive data plane.
 242  *
 243  */
 244 typedef struct
 245 {
 246   IxQMgrQId rxFreeQueue; /**< rxFree Queue for this port */
 247   IxEthAccPortRxCallback rxCallbackFn;
 248   UINT32  rxCallbackTag;
 249   IxEthAccDataPlaneQList freeBufferList;
 250   IxEthAccPortMultiBufferRxCallback rxMultiBufferCallbackFn;
 251   UINT32  rxMultiBufferCallbackTag;
 252   BOOL rxMultiBufferCallbackInUse;
 253   IxEthAccRxDataStats stats; /**< Receive s/w stats */
 254 } IxEthAccRxDataInfo;
 255
 256 /**
 257  * @struct  IxEthAccTxDataInfo
 258  * @brief   Per Port data structures associated with the transmit data plane.
 259  *
 260  */
 261 typedef struct
 262 {
 263   IxEthAccPortTxDoneCallback  txBufferDoneCallbackFn;
 264   UINT32  txCallbackTag;
 265   IxEthAccDataPlaneQList        txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */
 266   IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */
 267   IxQMgrQId txQueue; /**< txQueue for this port */
 268   IxEthAccTxDataStats stats; /**< Transmit s/w stats */
 269 } IxEthAccTxDataInfo;
 270
 271
 272 /**
 273  * @struct  IxEthAccPortDataInfo
 274  * @brief   Per Port data structures associated with the port data plane.
 275  *
 276  */
 277 typedef struct
 278 {
 279     BOOL               portInitialized;
 280     UINT32 npeId; /**< NpeId for this port */
 281     IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
 282     IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */
 283 } IxEthAccPortDataInfo;
 284
 285 extern IxEthAccPortDataInfo  ixEthAccPortData[];
 286 #define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized)
 287
 288 extern BOOL ixEthAccServiceInit;
 289 #define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == TRUE )
 290
 291 /*
 292  * Maximum number of frames to consume from the Rx Frame Q.
 293  */
 294
 295 #define IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK (128)
 296
 297 /*
 298  * Max number of times to load the Rx Free Q from callback.
 299  */
 300 #define IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD (256)  /* Set greater than depth of h/w Q + drain time at line rate */
 301
 302 /*
 303  *  Max number of times to read from the Tx Done Q in one sitting.
 304  */
 305
 306 #define IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK (256)
 307
 308 /*
 309  *  Max number of times to take buffers from S/w queues and write them to the H/w Tx
 310  *  queues on receipt of a Tx low threshold callback
 311  */
 312
 313 #define IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK (16)
 314
 315
 316 #define IX_ETH_ACC_FLUSH_CACHE(addr,size)  IX_OSAL_CACHE_FLUSH((addr),(size))
 317 #define IX_ETH_ACC_INVALIDATE_CACHE(addr,size)  IX_OSAL_CACHE_INVALIDATE((addr),(size))
 318
 319
 320 #define IX_ETH_ACC_MEMSET(start,value,size) memset(start,value,size)
 321
 322 #endif /* ndef IxEthAcc_p_H */
 323
 324
 325