arch/arm/cpu/ixp/start.S

   1 /* vi: set ts=8 sw=8 noet: */
   2 /*
   3  *  u-boot - Startup Code for XScale IXP
   4  *
   5  * Copyright (C) 2003   Kyle Harris <kharris@nexus-tech.net>
   6  *
   7  * Based on startup code example contained in the
   8  * Intel IXP4xx Programmer's Guide and past u-boot Start.S
   9  * samples.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <asm-offsets.h>
  31 #include <config.h>
  32 #include <version.h>
  33 #include <asm/arch/ixp425.h>
  34
  35 #define MMU_Control_M  0x001    /* Enable MMU */
  36 #define MMU_Control_A  0x002    /* Enable address alignment faults */
  37 #define MMU_Control_C  0x004    /* Enable cache */
  38 #define MMU_Control_W  0x008    /* Enable write-buffer */
  39 #define MMU_Control_P  0x010    /* Compatability: 32 bit code */
  40 #define MMU_Control_D  0x020    /* Compatability: 32 bit data */
  41 #define MMU_Control_L  0x040    /* Compatability: */
  42 #define MMU_Control_B  0x080    /* Enable Big-Endian */
  43 #define MMU_Control_S  0x100    /* Enable system protection */
  44 #define MMU_Control_R  0x200    /* Enable ROM protection */
  45 #define MMU_Control_I  0x1000   /* Enable Instruction cache */
  46 #define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
  47 #define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
  48
  49
  50 /*
  51  * Macro definitions
  52  */
  53         /* Delay a bit */
  54         .macro DELAY_FOR cycles, reg0
  55         ldr     \reg0, =\cycles
  56         subs    \reg0, \reg0, #1
  57         subne   pc,  pc, #0xc
  58         .endm
  59
  60         /* wait for coprocessor write complete */
  61         .macro CPWAIT reg
  62         mrc  p15,0,\reg,c2,c0,0
  63         mov  \reg,\reg
  64         sub  pc,pc,#4
  65         .endm
  66
  67 .globl _start
  68 _start:
  69         ldr     pc, _reset
  70         ldr     pc, _undefined_instruction
  71         ldr     pc, _software_interrupt
  72         ldr     pc, _prefetch_abort
  73         ldr     pc, _data_abort
  74         ldr     pc, _not_used
  75         ldr     pc, _irq
  76         ldr     pc, _fiq
  77
  78 _reset:                 .word reset
  79 _undefined_instruction: .word undefined_instruction
  80 _software_interrupt:    .word software_interrupt
  81 _prefetch_abort:        .word prefetch_abort
  82 _data_abort:            .word data_abort
  83 _not_used:              .word not_used
  84 _irq:                   .word irq
  85 _fiq:                   .word fiq
  86
  87         .balignl 16,0xdeadbeef
  88
  89
  90 /*
  91  * Startup Code (reset vector)
  92  *
  93  * do important init only if we don't start from memory!
  94  * - relocate armboot to ram
  95  * - setup stack
  96  * - jump to second stage
  97  */
  98
  99 .globl _TEXT_BASE
 100 _TEXT_BASE:
 101         .word   CONFIG_SYS_TEXT_BASE
 102
 103 /*
 104  * These are defined in the board-specific linker script.
 105  * Subtracting _start from them lets the linker put their
 106  * relative position in the executable instead of leaving
 107  * them null.
 108  */
 109 .globl _bss_start_ofs
 110 _bss_start_ofs:
 111         .word __bss_start - _start
 112
 113 .globl _bss_end_ofs
 114 _bss_end_ofs:
 115         .word __bss_end - _start
 116
 117 .globl _end_ofs
 118 _end_ofs:
 119         .word _end - _start
 120
 121 #ifdef CONFIG_USE_IRQ
 122 /* IRQ stack memory (calculated at run-time) */
 123 .globl IRQ_STACK_START
 124 IRQ_STACK_START:
 125         .word   0x0badc0de
 126
 127 /* IRQ stack memory (calculated at run-time) */
 128 .globl FIQ_STACK_START
 129 FIQ_STACK_START:
 130         .word 0x0badc0de
 131 #endif
 132
 133 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 134 .globl IRQ_STACK_START_IN
 135 IRQ_STACK_START_IN:
 136         .word   0x0badc0de
 137
 138 /*
 139  * the actual reset code
 140  */
 141
 142 reset:
 143         /* disable mmu, set big-endian */
 144         mov     r0, #0xf8
 145         mcr     p15, 0, r0, c1, c0, 0
 146         CPWAIT  r0
 147
 148         /* invalidate I & D caches & BTB */
 149         mcr     p15, 0, r0, c7, c7, 0
 150         CPWAIT  r0
 151
 152         /* invalidate I & Data TLB */
 153         mcr     p15, 0, r0, c8, c7, 0
 154         CPWAIT r0
 155
 156         /* drain write and fill buffers */
 157         mcr     p15, 0, r0, c7, c10, 4
 158         CPWAIT  r0
 159
 160         /* disable write buffer coalescing */
 161         mrc     p15, 0, r0, c1, c0, 1
 162         orr     r0, r0, #1
 163         mcr     p15, 0, r0, c1, c0, 1
 164         CPWAIT  r0
 165
 166         /* set EXP CS0 to the optimum timing */
 167         ldr     r1, =CONFIG_SYS_EXP_CS0
 168         ldr     r2, =IXP425_EXP_CS0
 169         str     r1, [r2]
 170
 171         /* make sure flash is visible at 0 */
 172         mov     r1, #CONFIG_SYS_SDR_CONFIG
 173         ldr     r2, =IXP425_SDR_CONFIG
 174         str     r1, [r2]
 175
 176         /* disable refresh cycles */
 177         mov     r1, #0
 178         ldr     r3, =IXP425_SDR_REFRESH
 179         str     r1, [r3]
 180
 181         /* send nop command */
 182         mov     r1, #3
 183         ldr     r4, =IXP425_SDR_IR
 184         str     r1, [r4]
 185         DELAY_FOR 0x4000, r0
 186
 187         /* set SDRAM internal refresh val */
 188         ldr     r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
 189         str     r1, [r3]
 190         DELAY_FOR 0x4000, r0
 191
 192         /* send precharge-all command to close all open banks */
 193         mov     r1, #2
 194         str     r1, [r4]
 195         DELAY_FOR 0x4000, r0
 196
 197         /* provide 8 auto-refresh cycles */
 198         mov     r1, #4
 199         mov     r5, #8
 200 111:    str     r1, [r4]
 201         DELAY_FOR 0x100, r0
 202         subs    r5, r5, #1
 203         bne     111b
 204
 205         /* set mode register in sdram */
 206         mov     r1, #CONFIG_SYS_SDR_MODE_CONFIG
 207         str     r1, [r4]
 208         DELAY_FOR 0x4000, r0
 209
 210         /* send normal operation command */
 211         mov     r1, #6
 212         str     r1, [r4]
 213         DELAY_FOR 0x4000, r0
 214
 215         /* invalidate I & D caches & BTB */
 216         mcr     p15, 0, r0, c7, c7, 0
 217         CPWAIT  r0
 218
 219         /* invalidate I & Data TLB */
 220         mcr     p15, 0, r0, c8, c7, 0
 221         CPWAIT r0
 222
 223         /* drain write and fill buffers */
 224         mcr     p15, 0, r0, c7, c10, 4
 225         CPWAIT  r0
 226
 227         /* remove flash mirror at 0x00000000 */
 228         ldr     r2, =IXP425_EXP_CFG0
 229         ldr     r1, [r2]
 230         bic     r1, r1, #0x80000000
 231         str     r1, [r2]
 232
 233         /* invalidate I & Data TLB */
 234         mcr     p15, 0, r0, c8, c7, 0
 235         CPWAIT r0
 236
 237         /* enable I cache */
 238         mrc     p15, 0, r0, c1, c0, 0
 239         orr     r0, r0, #MMU_Control_I
 240         mcr     p15, 0, r0, c1, c0, 0
 241         CPWAIT  r0
 242
 243         mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 244         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 245         orr     r0,r0,#0x13
 246         msr     cpsr,r0
 247
 248         bl      _main
 249
 250 /*------------------------------------------------------------------------------*/
 251
 252 /*
 253  * void relocate_code (addr_sp, gd, addr_moni)
 254  *
 255  * This "function" does not return, instead it continues in RAM
 256  * after relocating the monitor code.
 257  *
 258  */
 259         .globl  relocate_code
 260 relocate_code:
 261         mov     r4, r0  /* save addr_sp */
 262         mov     r5, r1  /* save addr of gd */
 263         mov     r6, r2  /* save addr of destination */
 264
 265         adr     r0, _start
 266         cmp     r0, r6
 267         moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
 268         beq     relocate_done           /* skip relocation */
 269         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 270         ldr     r3, _bss_start_ofs
 271         add     r2, r0, r3              /* r2 <- source end address         */
 272
 273 copy_loop:
 274         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 275         stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 276         cmp     r0, r2                  /* until source end address [r2]    */
 277         blo     copy_loop
 278
 279 #ifndef CONFIG_SPL_BUILD
 280         /*
 281          * fix .rel.dyn relocations
 282          */
 283         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 284         sub     r9, r6, r0              /* r9 <- relocation offset */
 285         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 286         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 287         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 288         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 289         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 290         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 291 fixloop:
 292         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 293         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 294         ldr     r1, [r2, #4]
 295         and     r7, r1, #0xff
 296         cmp     r7, #23                 /* relative fixup? */
 297         beq     fixrel
 298         cmp     r7, #2                  /* absolute fixup? */
 299         beq     fixabs
 300         /* ignore unknown type of fixup */
 301         b       fixnext
 302 fixabs:
 303         /* absolute fix: set location to (offset) symbol value */
 304         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 305         add     r1, r10, r1             /* r1 <- address of symbol in table */
 306         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 307         add     r1, r1, r9              /* r1 <- relocated sym addr */
 308         b       fixnext
 309 fixrel:
 310         /* relative fix: increase location by offset */
 311         ldr     r1, [r0]
 312         add     r1, r1, r9
 313 fixnext:
 314         str     r1, [r0]
 315         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 316         cmp     r2, r3
 317         blo     fixloop
 318 #endif
 319
 320 relocate_done:
 321
 322         bx      lr
 323
 324 _rel_dyn_start_ofs:
 325         .word __rel_dyn_start - _start
 326 _rel_dyn_end_ofs:
 327         .word __rel_dyn_end - _start
 328 _dynsym_start_ofs:
 329         .word __dynsym_start - _start
 330
 331         .globl  c_runtime_cpu_setup
 332 c_runtime_cpu_setup:
 333
 334         bx      lr
 335
 336 /****************************************************************************/
 337 /*                                                                          */
 338 /* Interrupt handling                                                       */
 339 /*                                                                          */
 340 /****************************************************************************/
 341
 342 /* IRQ stack frame                                                          */
 343
 344 #define S_FRAME_SIZE    72
 345
 346 #define S_OLD_R0        68
 347 #define S_PSR           64
 348 #define S_PC            60
 349 #define S_LR            56
 350 #define S_SP            52
 351
 352 #define S_IP            48
 353 #define S_FP            44
 354 #define S_R10           40
 355 #define S_R9            36
 356 #define S_R8            32
 357 #define S_R7            28
 358 #define S_R6            24
 359 #define S_R5            20
 360 #define S_R4            16
 361 #define S_R3            12
 362 #define S_R2            8
 363 #define S_R1            4
 364 #define S_R0            0
 365
 366 #define MODE_SVC 0x13
 367
 368         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 369
 370         .macro  bad_save_user_regs
 371         sub     sp, sp, #S_FRAME_SIZE
 372         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 373         add     r8, sp, #S_PC
 374
 375         ldr     r2, IRQ_STACK_START_IN
 376         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 377         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 378
 379         add     r5, sp, #S_SP
 380         mov     r1, lr
 381         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 382         mov     r0, sp
 383         .endm
 384
 385
 386         /* use irq_save_user_regs / irq_restore_user_regs for                */
 387         /* IRQ/FIQ handling                                                  */
 388
 389         .macro  irq_save_user_regs
 390         sub     sp, sp, #S_FRAME_SIZE
 391         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 392         add     r8, sp, #S_PC
 393         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 394         str     lr, [r8, #0]                    /* Save calling PC           */
 395         mrs     r6, spsr
 396         str     r6, [r8, #4]                    /* Save CPSR                 */
 397         str     r0, [r8, #8]                    /* Save OLD_R0               */
 398         mov     r0, sp
 399         .endm
 400
 401         .macro  irq_restore_user_regs
 402         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 403         mov     r0, r0
 404         ldr     lr, [sp, #S_PC]                 @ Get PC
 405         add     sp, sp, #S_FRAME_SIZE
 406         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 407         .endm
 408
 409         .macro get_bad_stack
 410         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 411
 412         str     lr, [r13]                       @ save caller lr / spsr
 413         mrs     lr, spsr
 414         str     lr, [r13, #4]
 415
 416         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 417         msr     spsr_c, r13
 418         mov     lr, pc
 419         movs    pc, lr
 420         .endm
 421
 422         .macro get_irq_stack                    @ setup IRQ stack
 423         ldr     sp, IRQ_STACK_START
 424         .endm
 425
 426         .macro get_fiq_stack                    @ setup FIQ stack
 427         ldr     sp, FIQ_STACK_START
 428         .endm
 429
 430
 431 /****************************************************************************/
 432 /*                                                                          */
 433 /* exception handlers                                                       */
 434 /*                                                                          */
 435 /****************************************************************************/
 436
 437         .align  5
 438 undefined_instruction:
 439         get_bad_stack
 440         bad_save_user_regs
 441         bl      do_undefined_instruction
 442
 443         .align  5
 444 software_interrupt:
 445         get_bad_stack
 446         bad_save_user_regs
 447         bl      do_software_interrupt
 448
 449         .align  5
 450 prefetch_abort:
 451         get_bad_stack
 452         bad_save_user_regs
 453         bl      do_prefetch_abort
 454
 455         .align  5
 456 data_abort:
 457         get_bad_stack
 458         bad_save_user_regs
 459         bl      do_data_abort
 460
 461         .align  5
 462 not_used:
 463         get_bad_stack
 464         bad_save_user_regs
 465         bl      do_not_used
 466
 467 #ifdef CONFIG_USE_IRQ
 468
 469         .align  5
 470 irq:
 471         get_irq_stack
 472         irq_save_user_regs
 473         bl      do_irq
 474         irq_restore_user_regs
 475
 476         .align  5
 477 fiq:
 478         get_fiq_stack
 479         irq_save_user_regs              /* someone ought to write a more    */
 480         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 481         irq_restore_user_regs
 482
 483 #else
 484
 485         .align  5
 486 irq:
 487         get_bad_stack
 488         bad_save_user_regs
 489         bl      do_irq
 490
 491         .align  5
 492 fiq:
 493         get_bad_stack
 494         bad_save_user_regs
 495         bl      do_fiq
 496
 497 #endif
 498
 499 /****************************************************************************/
 500 /*                                                                          */
 501 /* Reset function: Use Watchdog to reset                                    */
 502 /*                                                                          */
 503 /****************************************************************************/
 504
 505         .align  5
 506 .globl reset_cpu
 507
 508 reset_cpu:
 509         ldr     r1, =0x482e
 510         ldr     r2, =IXP425_OSWK
 511         str     r1, [r2]
 512         ldr     r1, =0x0fff
 513         ldr     r2, =IXP425_OSWT
 514         str     r1, [r2]
 515         ldr     r1, =0x5
 516         ldr     r2, =IXP425_OSWE
 517         str     r1, [r2]
 518         b       reset_endless
 519
 520 reset_endless:
 521         b       reset_endless