arch/arm/cpu/ixp/start.S

   1 /* vi: set ts=8 sw=8 noet: */
   2 /*
   3  *  u-boot - Startup Code for XScale IXP
   4  *
   5  * Copyright (C) 2003   Kyle Harris <kharris@nexus-tech.net>
   6  *
   7  * Based on startup code example contained in the
   8  * Intel IXP4xx Programmer's Guide and past u-boot Start.S
   9  * samples.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <asm-offsets.h>
  31 #include <config.h>
  32 #include <version.h>
  33 #include <asm/arch/ixp425.h>
  34
  35 #define MMU_Control_M  0x001    /* Enable MMU */
  36 #define MMU_Control_A  0x002    /* Enable address alignment faults */
  37 #define MMU_Control_C  0x004    /* Enable cache */
  38 #define MMU_Control_W  0x008    /* Enable write-buffer */
  39 #define MMU_Control_P  0x010    /* Compatability: 32 bit code */
  40 #define MMU_Control_D  0x020    /* Compatability: 32 bit data */
  41 #define MMU_Control_L  0x040    /* Compatability: */
  42 #define MMU_Control_B  0x080    /* Enable Big-Endian */
  43 #define MMU_Control_S  0x100    /* Enable system protection */
  44 #define MMU_Control_R  0x200    /* Enable ROM protection */
  45 #define MMU_Control_I  0x1000   /* Enable Instruction cache */
  46 #define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
  47 #define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
  48
  49
  50 /*
  51  * Macro definitions
  52  */
  53         /* Delay a bit */
  54         .macro DELAY_FOR cycles, reg0
  55         ldr     \reg0, =\cycles
  56         subs    \reg0, \reg0, #1
  57         subne   pc,  pc, #0xc
  58         .endm
  59
  60         /* wait for coprocessor write complete */
  61         .macro CPWAIT reg
  62         mrc  p15,0,\reg,c2,c0,0
  63         mov  \reg,\reg
  64         sub  pc,pc,#4
  65         .endm
  66
  67 .globl _start
  68 _start: b       reset
  69         ldr     pc, _undefined_instruction
  70         ldr     pc, _software_interrupt
  71         ldr     pc, _prefetch_abort
  72         ldr     pc, _data_abort
  73         ldr     pc, _not_used
  74         ldr     pc, _irq
  75         ldr     pc, _fiq
  76
  77 _undefined_instruction: .word undefined_instruction
  78 _software_interrupt:    .word software_interrupt
  79 _prefetch_abort:        .word prefetch_abort
  80 _data_abort:            .word data_abort
  81 _not_used:              .word not_used
  82 _irq:                   .word irq
  83 _fiq:                   .word fiq
  84
  85         .balignl 16,0xdeadbeef
  86
  87
  88 /*
  89  * Startup Code (reset vector)
  90  *
  91  * do important init only if we don't start from memory!
  92  * - relocate armboot to ram
  93  * - setup stack
  94  * - jump to second stage
  95  */
  96
  97 .globl _TEXT_BASE
  98 _TEXT_BASE:
  99         .word   CONFIG_SYS_TEXT_BASE
 100
 101 /*
 102  * These are defined in the board-specific linker script.
 103  * Subtracting _start from them lets the linker put their
 104  * relative position in the executable instead of leaving
 105  * them null.
 106  */
 107 .globl _bss_start_ofs
 108 _bss_start_ofs:
 109         .word __bss_start - _start
 110
 111 .globl _bss_end_ofs
 112 _bss_end_ofs:
 113         .word _end - _start
 114
 115 #ifdef CONFIG_USE_IRQ
 116 /* IRQ stack memory (calculated at run-time) */
 117 .globl IRQ_STACK_START
 118 IRQ_STACK_START:
 119         .word   0x0badc0de
 120
 121 /* IRQ stack memory (calculated at run-time) */
 122 .globl FIQ_STACK_START
 123 FIQ_STACK_START:
 124         .word 0x0badc0de
 125 #endif
 126
 127 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 128 .globl IRQ_STACK_START_IN
 129 IRQ_STACK_START_IN:
 130         .word   0x0badc0de
 131
 132 /*
 133  * the actual reset code
 134  */
 135
 136 reset:
 137         /* disable mmu, set big-endian */
 138         mov     r0, #0xf8
 139         mcr     p15, 0, r0, c1, c0, 0
 140         CPWAIT  r0
 141
 142         /* invalidate I & D caches & BTB */
 143         mcr     p15, 0, r0, c7, c7, 0
 144         CPWAIT  r0
 145
 146         /* invalidate I & Data TLB */
 147         mcr     p15, 0, r0, c8, c7, 0
 148         CPWAIT r0
 149
 150         /* drain write and fill buffers */
 151         mcr     p15, 0, r0, c7, c10, 4
 152         CPWAIT  r0
 153
 154         /* disable write buffer coalescing */
 155         mrc     p15, 0, r0, c1, c0, 1
 156         orr     r0, r0, #1
 157         mcr     p15, 0, r0, c1, c0, 1
 158         CPWAIT  r0
 159
 160         /* set EXP CS0 to the optimum timing */
 161         ldr     r1, =CONFIG_SYS_EXP_CS0
 162         ldr     r2, =IXP425_EXP_CS0
 163         str     r1, [r2]
 164
 165         /* make sure flash is visible at 0 */
 166 #if 0
 167         ldr     r2, =IXP425_EXP_CFG0
 168         ldr     r1, [r2]
 169         orr     r1, r1, #0x80000000
 170         str     r1, [r2]
 171 #endif
 172         mov     r1, #CONFIG_SYS_SDR_CONFIG
 173         ldr     r2, =IXP425_SDR_CONFIG
 174         str     r1, [r2]
 175
 176         /* disable refresh cycles */
 177         mov     r1, #0
 178         ldr     r3, =IXP425_SDR_REFRESH
 179         str     r1, [r3]
 180
 181         /* send nop command */
 182         mov     r1, #3
 183         ldr     r4, =IXP425_SDR_IR
 184         str     r1, [r4]
 185         DELAY_FOR 0x4000, r0
 186
 187         /* set SDRAM internal refresh val */
 188         ldr     r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
 189         str     r1, [r3]
 190         DELAY_FOR 0x4000, r0
 191
 192         /* send precharge-all command to close all open banks */
 193         mov     r1, #2
 194         str     r1, [r4]
 195         DELAY_FOR 0x4000, r0
 196
 197         /* provide 8 auto-refresh cycles */
 198         mov     r1, #4
 199         mov     r5, #8
 200 111:    str     r1, [r4]
 201         DELAY_FOR 0x100, r0
 202         subs    r5, r5, #1
 203         bne     111b
 204
 205         /* set mode register in sdram */
 206         mov     r1, #CONFIG_SYS_SDR_MODE_CONFIG
 207         str     r1, [r4]
 208         DELAY_FOR 0x4000, r0
 209
 210         /* send normal operation command */
 211         mov     r1, #6
 212         str     r1, [r4]
 213         DELAY_FOR 0x4000, r0
 214
 215         /* copy */
 216         mov     r0, #0
 217         mov     r4, r0
 218         add     r2, r0, #CONFIG_SYS_MONITOR_LEN
 219         mov     r1, #0x10000000
 220         mov     r5, r1
 221
 222     30:
 223         ldr     r3, [r0], #4
 224         str     r3, [r1], #4
 225         cmp     r0, r2
 226         bne     30b
 227
 228         /* invalidate I & D caches & BTB */
 229         mcr     p15, 0, r0, c7, c7, 0
 230         CPWAIT  r0
 231
 232         /* invalidate I & Data TLB */
 233         mcr     p15, 0, r0, c8, c7, 0
 234         CPWAIT r0
 235
 236         /* drain write and fill buffers */
 237         mcr     p15, 0, r0, c7, c10, 4
 238         CPWAIT  r0
 239
 240         /* move flash to 0x50000000 */
 241         ldr     r2, =IXP425_EXP_CFG0
 242         ldr     r1, [r2]
 243         bic     r1, r1, #0x80000000
 244         str     r1, [r2]
 245
 246         nop
 247         nop
 248         nop
 249         nop
 250         nop
 251         nop
 252
 253         /* invalidate I & Data TLB */
 254         mcr     p15, 0, r0, c8, c7, 0
 255         CPWAIT r0
 256
 257         /* enable I cache */
 258         mrc     p15, 0, r0, c1, c0, 0
 259         orr     r0, r0, #MMU_Control_I
 260         mcr     p15, 0, r0, c1, c0, 0
 261         CPWAIT  r0
 262
 263         mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 264         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 265         orr     r0,r0,#0x13
 266         msr     cpsr,r0
 267
 268 /* Set stackpointer in internal RAM to call board_init_f */
 269 call_board_init_f:
 270         ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 271         bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
 272         ldr     r0,=0x00000000
 273         bl      board_init_f
 274
 275 /*------------------------------------------------------------------------------*/
 276
 277 /*
 278  * void relocate_code (addr_sp, gd, addr_moni)
 279  *
 280  * This "function" does not return, instead it continues in RAM
 281  * after relocating the monitor code.
 282  *
 283  */
 284         .globl  relocate_code
 285 relocate_code:
 286         mov     r4, r0  /* save addr_sp */
 287         mov     r5, r1  /* save addr of gd */
 288         mov     r6, r2  /* save addr of destination */
 289
 290         /* Set up the stack                                                 */
 291 stack_setup:
 292         mov     sp, r4
 293
 294         adr     r0, _start
 295         cmp     r0, r6
 296         beq     clear_bss               /* skip relocation */
 297         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 298         ldr     r2, _TEXT_BASE
 299         ldr     r3, _bss_start_ofs
 300         add     r2, r0, r3              /* r2 <- source end address         */
 301
 302 copy_loop:
 303         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 304         stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 305         cmp     r0, r2                  /* until source end address [r2]    */
 306         blo     copy_loop
 307
 308 #ifndef CONFIG_PRELOADER
 309         /*
 310          * fix .rel.dyn relocations
 311          */
 312         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 313         sub     r9, r6, r0              /* r9 <- relocation offset */
 314         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 315         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 316         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 317         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 318         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 319         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 320 fixloop:
 321         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 322         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 323         ldr     r1, [r2, #4]
 324         and     r8, r1, #0xff
 325         cmp     r8, #23                 /* relative fixup? */
 326         beq     fixrel
 327         cmp     r8, #2                  /* absolute fixup? */
 328         beq     fixabs
 329         /* ignore unknown type of fixup */
 330         b       fixnext
 331 fixabs:
 332         /* absolute fix: set location to (offset) symbol value */
 333         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 334         add     r1, r10, r1             /* r1 <- address of symbol in table */
 335         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 336         add     r1, r9                  /* r1 <- relocated sym addr */
 337         b       fixnext
 338 fixrel:
 339         /* relative fix: increase location by offset */
 340         ldr     r1, [r0]
 341         add     r1, r1, r9
 342 fixnext:
 343         str     r1, [r0]
 344         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 345         cmp     r2, r3
 346         blo     fixloop
 347 #endif
 348
 349 clear_bss:
 350 #ifndef CONFIG_PRELOADER
 351         ldr     r0, _bss_start_ofs
 352         ldr     r1, _bss_end_ofs
 353         ldr     r3, _TEXT_BASE          /* Text base */
 354         mov     r4, r6                  /* reloc addr */
 355         add     r0, r0, r4
 356         add     r1, r1, r4
 357         mov     r2, #0x00000000         /* clear                            */
 358
 359 clbss_l:str     r2, [r0]                /* clear loop...                    */
 360         add     r0, r0, #4
 361         cmp     r0, r1
 362         bne     clbss_l
 363
 364         bl coloured_LED_init
 365         bl red_LED_on
 366 #endif
 367
 368 /*
 369  * We are done. Do not return, instead branch to second part of board
 370  * initialization, now running from RAM.
 371  */
 372         ldr     r0, _board_init_r_ofs
 373         adr     r1, _start
 374         add     lr, r0, r1
 375         add     lr, lr, r9
 376         /* setup parameters for board_init_r */
 377         mov     r0, r5          /* gd_t */
 378         mov     r1, r6          /* dest_addr */
 379         /* jump to it ... */
 380         mov     pc, lr
 381
 382 _board_init_r_ofs:
 383         .word board_init_r - _start
 384
 385 _rel_dyn_start_ofs:
 386         .word __rel_dyn_start - _start
 387 _rel_dyn_end_ofs:
 388         .word __rel_dyn_end - _start
 389 _dynsym_start_ofs:
 390         .word __dynsym_start - _start
 391
 392 /****************************************************************************/
 393 /*                                                                          */
 394 /* Interrupt handling                                                       */
 395 /*                                                                          */
 396 /****************************************************************************/
 397
 398 /* IRQ stack frame                                                          */
 399
 400 #define S_FRAME_SIZE    72
 401
 402 #define S_OLD_R0        68
 403 #define S_PSR           64
 404 #define S_PC            60
 405 #define S_LR            56
 406 #define S_SP            52
 407
 408 #define S_IP            48
 409 #define S_FP            44
 410 #define S_R10           40
 411 #define S_R9            36
 412 #define S_R8            32
 413 #define S_R7            28
 414 #define S_R6            24
 415 #define S_R5            20
 416 #define S_R4            16
 417 #define S_R3            12
 418 #define S_R2            8
 419 #define S_R1            4
 420 #define S_R0            0
 421
 422 #define MODE_SVC 0x13
 423
 424         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 425
 426         .macro  bad_save_user_regs
 427         sub     sp, sp, #S_FRAME_SIZE
 428         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 429         add     r8, sp, #S_PC
 430
 431         ldr     r2, IRQ_STACK_START_IN
 432         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 433         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 434
 435         add     r5, sp, #S_SP
 436         mov     r1, lr
 437         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 438         mov     r0, sp
 439         .endm
 440
 441
 442         /* use irq_save_user_regs / irq_restore_user_regs for                */
 443         /* IRQ/FIQ handling                                                  */
 444
 445         .macro  irq_save_user_regs
 446         sub     sp, sp, #S_FRAME_SIZE
 447         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 448         add     r8, sp, #S_PC
 449         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 450         str     lr, [r8, #0]                    /* Save calling PC           */
 451         mrs     r6, spsr
 452         str     r6, [r8, #4]                    /* Save CPSR                 */
 453         str     r0, [r8, #8]                    /* Save OLD_R0               */
 454         mov     r0, sp
 455         .endm
 456
 457         .macro  irq_restore_user_regs
 458         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 459         mov     r0, r0
 460         ldr     lr, [sp, #S_PC]                 @ Get PC
 461         add     sp, sp, #S_FRAME_SIZE
 462         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 463         .endm
 464
 465         .macro get_bad_stack
 466         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 467
 468         str     lr, [r13]                       @ save caller lr / spsr
 469         mrs     lr, spsr
 470         str     lr, [r13, #4]
 471
 472         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 473         msr     spsr_c, r13
 474         mov     lr, pc
 475         movs    pc, lr
 476         .endm
 477
 478         .macro get_irq_stack                    @ setup IRQ stack
 479         ldr     sp, IRQ_STACK_START
 480         .endm
 481
 482         .macro get_fiq_stack                    @ setup FIQ stack
 483         ldr     sp, FIQ_STACK_START
 484         .endm
 485
 486
 487 /****************************************************************************/
 488 /*                                                                          */
 489 /* exception handlers                                                       */
 490 /*                                                                          */
 491 /****************************************************************************/
 492
 493         .align  5
 494 undefined_instruction:
 495         get_bad_stack
 496         bad_save_user_regs
 497         bl      do_undefined_instruction
 498
 499         .align  5
 500 software_interrupt:
 501         get_bad_stack
 502         bad_save_user_regs
 503         bl      do_software_interrupt
 504
 505         .align  5
 506 prefetch_abort:
 507         get_bad_stack
 508         bad_save_user_regs
 509         bl      do_prefetch_abort
 510
 511         .align  5
 512 data_abort:
 513         get_bad_stack
 514         bad_save_user_regs
 515         bl      do_data_abort
 516
 517         .align  5
 518 not_used:
 519         get_bad_stack
 520         bad_save_user_regs
 521         bl      do_not_used
 522
 523 #ifdef CONFIG_USE_IRQ
 524
 525         .align  5
 526 irq:
 527         get_irq_stack
 528         irq_save_user_regs
 529         bl      do_irq
 530         irq_restore_user_regs
 531
 532         .align  5
 533 fiq:
 534         get_fiq_stack
 535         irq_save_user_regs              /* someone ought to write a more    */
 536         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 537         irq_restore_user_regs
 538
 539 #else
 540
 541         .align  5
 542 irq:
 543         get_bad_stack
 544         bad_save_user_regs
 545         bl      do_irq
 546
 547         .align  5
 548 fiq:
 549         get_bad_stack
 550         bad_save_user_regs
 551         bl      do_fiq
 552
 553 #endif
 554
 555 /****************************************************************************/
 556 /*                                                                          */
 557 /* Reset function: Use Watchdog to reset                                    */
 558 /*                                                                          */
 559 /****************************************************************************/
 560
 561         .align  5
 562 .globl reset_cpu
 563
 564 reset_cpu:
 565         ldr     r1, =0x482e
 566         ldr     r2, =IXP425_OSWK
 567         str     r1, [r2]
 568         ldr     r1, =0x0fff
 569         ldr     r2, =IXP425_OSWT
 570         str     r1, [r2]
 571         ldr     r1, =0x5
 572         ldr     r2, =IXP425_OSWE
 573         str     r1, [r2]
 574         b       reset_endless
 575
 576
 577 reset_endless:
 578
 579         b       reset_endless
 580
 581 #ifdef CONFIG_USE_IRQ
 582
 583 .LC0:           .word   loops_per_jiffy
 584
 585 /*
 586  * 0 <= r0 <= 2000
 587  */
 588 .globl __udelay
 589 __udelay:
 590         mov     r2,     #0x6800
 591         orr     r2, r2, #0x00db
 592         mul     r0, r2, r0
 593         ldr     r2, .LC0
 594         ldr     r2, [r2]                @ max = 0x0fffffff
 595         mov     r0, r0, lsr #11         @ max = 0x00003fff
 596         mov     r2, r2, lsr #11         @ max = 0x0003ffff
 597         mul     r0, r2, r0              @ max = 2^32-1
 598         movs    r0, r0, lsr #6
 599
 600 delay_loop:
 601         subs    r0, r0, #1
 602         bne     delay_loop
 603         mov     pc, lr
 604
 605 #endif /* CONFIG_USE_IRQ */