arch/arm/cpu/ixp/start.S

   1 /* vi: set ts=8 sw=8 noet: */
   2 /*
   3  *  u-boot - Startup Code for XScale IXP
   4  *
   5  * Copyright (C) 2003   Kyle Harris <kharris@nexus-tech.net>
   6  *
   7  * Based on startup code example contained in the
   8  * Intel IXP4xx Programmer's Guide and past u-boot Start.S
   9  * samples.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <asm-offsets.h>
  31 #include <config.h>
  32 #include <version.h>
  33 #include <asm/arch/ixp425.h>
  34
  35 #define MMU_Control_M  0x001    /* Enable MMU */
  36 #define MMU_Control_A  0x002    /* Enable address alignment faults */
  37 #define MMU_Control_C  0x004    /* Enable cache */
  38 #define MMU_Control_W  0x008    /* Enable write-buffer */
  39 #define MMU_Control_P  0x010    /* Compatability: 32 bit code */
  40 #define MMU_Control_D  0x020    /* Compatability: 32 bit data */
  41 #define MMU_Control_L  0x040    /* Compatability: */
  42 #define MMU_Control_B  0x080    /* Enable Big-Endian */
  43 #define MMU_Control_S  0x100    /* Enable system protection */
  44 #define MMU_Control_R  0x200    /* Enable ROM protection */
  45 #define MMU_Control_I  0x1000   /* Enable Instruction cache */
  46 #define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
  47 #define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
  48
  49
  50 /*
  51  * Macro definitions
  52  */
  53         /* Delay a bit */
  54         .macro DELAY_FOR cycles, reg0
  55         ldr     \reg0, =\cycles
  56         subs    \reg0, \reg0, #1
  57         subne   pc,  pc, #0xc
  58         .endm
  59
  60         /* wait for coprocessor write complete */
  61         .macro CPWAIT reg
  62         mrc  p15,0,\reg,c2,c0,0
  63         mov  \reg,\reg
  64         sub  pc,pc,#4
  65         .endm
  66
  67 .globl _start
  68 _start: b       reset
  69         ldr     pc, _undefined_instruction
  70         ldr     pc, _software_interrupt
  71         ldr     pc, _prefetch_abort
  72         ldr     pc, _data_abort
  73         ldr     pc, _not_used
  74         ldr     pc, _irq
  75         ldr     pc, _fiq
  76
  77 _undefined_instruction: .word undefined_instruction
  78 _software_interrupt:    .word software_interrupt
  79 _prefetch_abort:        .word prefetch_abort
  80 _data_abort:            .word data_abort
  81 _not_used:              .word not_used
  82 _irq:                   .word irq
  83 _fiq:                   .word fiq
  84
  85         .balignl 16,0xdeadbeef
  86
  87
  88 /*
  89  * Startup Code (reset vector)
  90  *
  91  * do important init only if we don't start from memory!
  92  * - relocate armboot to ram
  93  * - setup stack
  94  * - jump to second stage
  95  */
  96
  97 .globl _TEXT_BASE
  98 _TEXT_BASE:
  99         .word   CONFIG_SYS_TEXT_BASE
 100
 101 /*
 102  * These are defined in the board-specific linker script.
 103  */
 104 .globl _bss_start
 105 _bss_start:
 106         .word __bss_start
 107
 108 .globl _bss_end
 109 _bss_end:
 110         .word _end
 111
 112 #ifdef CONFIG_USE_IRQ
 113 /* IRQ stack memory (calculated at run-time) */
 114 .globl IRQ_STACK_START
 115 IRQ_STACK_START:
 116         .word   0x0badc0de
 117
 118 /* IRQ stack memory (calculated at run-time) */
 119 .globl FIQ_STACK_START
 120 FIQ_STACK_START:
 121         .word 0x0badc0de
 122 #endif
 123
 124 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 125 .globl IRQ_STACK_START_IN
 126 IRQ_STACK_START_IN:
 127         .word   0x0badc0de
 128
 129 .globl _datarel_start
 130 _datarel_start:
 131         .word __datarel_start
 132
 133 .globl _datarelrolocal_start
 134 _datarelrolocal_start:
 135         .word __datarelrolocal_start
 136
 137 .globl _datarellocal_start
 138 _datarellocal_start:
 139         .word __datarellocal_start
 140
 141 .globl _datarelro_start
 142 _datarelro_start:
 143         .word __datarelro_start
 144
 145 .globl _got_start
 146 _got_start:
 147         .word __got_start
 148
 149 .globl _got_end
 150 _got_end:
 151         .word __got_end
 152
 153 /*
 154  * the actual reset code
 155  */
 156
 157 reset:
 158         /* disable mmu, set big-endian */
 159         mov     r0, #0xf8
 160         mcr     p15, 0, r0, c1, c0, 0
 161         CPWAIT  r0
 162
 163         /* invalidate I & D caches & BTB */
 164         mcr     p15, 0, r0, c7, c7, 0
 165         CPWAIT  r0
 166
 167         /* invalidate I & Data TLB */
 168         mcr     p15, 0, r0, c8, c7, 0
 169         CPWAIT r0
 170
 171         /* drain write and fill buffers */
 172         mcr     p15, 0, r0, c7, c10, 4
 173         CPWAIT  r0
 174
 175         /* disable write buffer coalescing */
 176         mrc     p15, 0, r0, c1, c0, 1
 177         orr     r0, r0, #1
 178         mcr     p15, 0, r0, c1, c0, 1
 179         CPWAIT  r0
 180
 181         /* set EXP CS0 to the optimum timing */
 182         ldr     r1, =CONFIG_SYS_EXP_CS0
 183         ldr     r2, =IXP425_EXP_CS0
 184         str     r1, [r2]
 185
 186         /* make sure flash is visible at 0 */
 187 #if 0
 188         ldr     r2, =IXP425_EXP_CFG0
 189         ldr     r1, [r2]
 190         orr     r1, r1, #0x80000000
 191         str     r1, [r2]
 192 #endif
 193         mov     r1, #CONFIG_SYS_SDR_CONFIG
 194         ldr     r2, =IXP425_SDR_CONFIG
 195         str     r1, [r2]
 196
 197         /* disable refresh cycles */
 198         mov     r1, #0
 199         ldr     r3, =IXP425_SDR_REFRESH
 200         str     r1, [r3]
 201
 202         /* send nop command */
 203         mov     r1, #3
 204         ldr     r4, =IXP425_SDR_IR
 205         str     r1, [r4]
 206         DELAY_FOR 0x4000, r0
 207
 208         /* set SDRAM internal refresh val */
 209         ldr     r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
 210         str     r1, [r3]
 211         DELAY_FOR 0x4000, r0
 212
 213         /* send precharge-all command to close all open banks */
 214         mov     r1, #2
 215         str     r1, [r4]
 216         DELAY_FOR 0x4000, r0
 217
 218         /* provide 8 auto-refresh cycles */
 219         mov     r1, #4
 220         mov     r5, #8
 221 111:    str     r1, [r4]
 222         DELAY_FOR 0x100, r0
 223         subs    r5, r5, #1
 224         bne     111b
 225
 226         /* set mode register in sdram */
 227         mov     r1, #CONFIG_SYS_SDR_MODE_CONFIG
 228         str     r1, [r4]
 229         DELAY_FOR 0x4000, r0
 230
 231         /* send normal operation command */
 232         mov     r1, #6
 233         str     r1, [r4]
 234         DELAY_FOR 0x4000, r0
 235
 236         /* copy */
 237         mov     r0, #0
 238         mov     r4, r0
 239         add     r2, r0, #CONFIG_SYS_MONITOR_LEN
 240         mov     r1, #0x10000000
 241         mov     r5, r1
 242
 243     30:
 244         ldr     r3, [r0], #4
 245         str     r3, [r1], #4
 246         cmp     r0, r2
 247         bne     30b
 248
 249         /* invalidate I & D caches & BTB */
 250         mcr     p15, 0, r0, c7, c7, 0
 251         CPWAIT  r0
 252
 253         /* invalidate I & Data TLB */
 254         mcr     p15, 0, r0, c8, c7, 0
 255         CPWAIT r0
 256
 257         /* drain write and fill buffers */
 258         mcr     p15, 0, r0, c7, c10, 4
 259         CPWAIT  r0
 260
 261         /* move flash to 0x50000000 */
 262         ldr     r2, =IXP425_EXP_CFG0
 263         ldr     r1, [r2]
 264         bic     r1, r1, #0x80000000
 265         str     r1, [r2]
 266
 267         nop
 268         nop
 269         nop
 270         nop
 271         nop
 272         nop
 273
 274         /* invalidate I & Data TLB */
 275         mcr     p15, 0, r0, c8, c7, 0
 276         CPWAIT r0
 277
 278         /* enable I cache */
 279         mrc     p15, 0, r0, c1, c0, 0
 280         orr     r0, r0, #MMU_Control_I
 281         mcr     p15, 0, r0, c1, c0, 0
 282         CPWAIT  r0
 283
 284         mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 285         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 286         orr     r0,r0,#0x13
 287         msr     cpsr,r0
 288
 289 /* Set stackpointer in internal RAM to call board_init_f */
 290 call_board_init_f:
 291         ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 292         ldr     r0,=0x00000000
 293         bl      board_init_f
 294
 295 /*------------------------------------------------------------------------------*/
 296
 297 /*
 298  * void relocate_code (addr_sp, gd, addr_moni)
 299  *
 300  * This "function" does not return, instead it continues in RAM
 301  * after relocating the monitor code.
 302  *
 303  */
 304         .globl  relocate_code
 305 relocate_code:
 306         mov     r4, r0  /* save addr_sp */
 307         mov     r5, r1  /* save addr of gd */
 308         mov     r6, r2  /* save addr of destination */
 309         mov     r7, r2  /* save addr of destination */
 310
 311         /* Set up the stack                                                 */
 312 stack_setup:
 313         mov     sp, r4
 314
 315         adr     r0, _start
 316         ldr     r2, _TEXT_BASE
 317         ldr     r3, _bss_start
 318         sub     r2, r3, r2              /* r2 <- size of armboot            */
 319         add     r2, r0, r2              /* r2 <- source end address         */
 320         cmp     r0, r6
 321         beq     clear_bss
 322
 323 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 324 copy_loop:
 325         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 326         stmia   r6!, {r9-r10}           /* copy to   target address [r1]    */
 327         cmp     r0, r2                  /* until source end address [r2]    */
 328         blo     copy_loop
 329
 330 #ifndef CONFIG_PRELOADER
 331         /* fix got entries */
 332         ldr     r1, _TEXT_BASE          /* Text base */
 333         mov     r0, r7                  /* reloc addr */
 334         ldr     r2, _got_start          /* addr in Flash */
 335         ldr     r3, _got_end            /* addr in Flash */
 336         sub     r3, r3, r1
 337         add     r3, r3, r0
 338         sub     r2, r2, r1
 339         add     r2, r2, r0
 340
 341 fixloop:
 342         ldr     r4, [r2]
 343         sub     r4, r4, r1
 344         add     r4, r4, r0
 345         str     r4, [r2]
 346         add     r2, r2, #4
 347         cmp     r2, r3
 348         blo     fixloop
 349 #endif
 350 #endif  /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 351
 352 clear_bss:
 353 #ifndef CONFIG_PRELOADER
 354         ldr     r0, _bss_start
 355         ldr     r1, _bss_end
 356         ldr     r3, _TEXT_BASE          /* Text base */
 357         mov     r4, r7                  /* reloc addr */
 358         sub     r0, r0, r3
 359         add     r0, r0, r4
 360         sub     r1, r1, r3
 361         add     r1, r1, r4
 362         mov     r2, #0x00000000         /* clear                            */
 363
 364 clbss_l:str     r2, [r0]                /* clear loop...                    */
 365         add     r0, r0, #4
 366         cmp     r0, r1
 367         bne     clbss_l
 368
 369         bl coloured_LED_init
 370         bl red_LED_on
 371 #endif
 372
 373 /*
 374  * We are done. Do not return, instead branch to second part of board
 375  * initialization, now running from RAM.
 376  */
 377         ldr     r0, _TEXT_BASE
 378         ldr     r2, _board_init_r
 379         sub     r2, r2, r0
 380         add     r2, r2, r7      /* position from board_init_r in RAM */
 381         /* setup parameters for board_init_r */
 382         mov     r0, r5          /* gd_t */
 383         mov     r1, r7          /* dest_addr */
 384         /* jump to it ... */
 385         mov     lr, r2
 386         mov     pc, lr
 387
 388 _board_init_r: .word board_init_r
 389
 390
 391 /****************************************************************************/
 392 /*                                                                          */
 393 /* Interrupt handling                                                       */
 394 /*                                                                          */
 395 /****************************************************************************/
 396
 397 /* IRQ stack frame                                                          */
 398
 399 #define S_FRAME_SIZE    72
 400
 401 #define S_OLD_R0        68
 402 #define S_PSR           64
 403 #define S_PC            60
 404 #define S_LR            56
 405 #define S_SP            52
 406
 407 #define S_IP            48
 408 #define S_FP            44
 409 #define S_R10           40
 410 #define S_R9            36
 411 #define S_R8            32
 412 #define S_R7            28
 413 #define S_R6            24
 414 #define S_R5            20
 415 #define S_R4            16
 416 #define S_R3            12
 417 #define S_R2            8
 418 #define S_R1            4
 419 #define S_R0            0
 420
 421 #define MODE_SVC 0x13
 422
 423         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 424
 425         .macro  bad_save_user_regs
 426         sub     sp, sp, #S_FRAME_SIZE
 427         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 428         add     r8, sp, #S_PC
 429
 430         ldr     r2, IRQ_STACK_START_IN
 431         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 432         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 433
 434         add     r5, sp, #S_SP
 435         mov     r1, lr
 436         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 437         mov     r0, sp
 438         .endm
 439
 440
 441         /* use irq_save_user_regs / irq_restore_user_regs for                */
 442         /* IRQ/FIQ handling                                                  */
 443
 444         .macro  irq_save_user_regs
 445         sub     sp, sp, #S_FRAME_SIZE
 446         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 447         add     r8, sp, #S_PC
 448         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 449         str     lr, [r8, #0]                    /* Save calling PC           */
 450         mrs     r6, spsr
 451         str     r6, [r8, #4]                    /* Save CPSR                 */
 452         str     r0, [r8, #8]                    /* Save OLD_R0               */
 453         mov     r0, sp
 454         .endm
 455
 456         .macro  irq_restore_user_regs
 457         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 458         mov     r0, r0
 459         ldr     lr, [sp, #S_PC]                 @ Get PC
 460         add     sp, sp, #S_FRAME_SIZE
 461         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 462         .endm
 463
 464         .macro get_bad_stack
 465         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 466
 467         str     lr, [r13]                       @ save caller lr / spsr
 468         mrs     lr, spsr
 469         str     lr, [r13, #4]
 470
 471         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 472         msr     spsr_c, r13
 473         mov     lr, pc
 474         movs    pc, lr
 475         .endm
 476
 477         .macro get_irq_stack                    @ setup IRQ stack
 478         ldr     sp, IRQ_STACK_START
 479         .endm
 480
 481         .macro get_fiq_stack                    @ setup FIQ stack
 482         ldr     sp, FIQ_STACK_START
 483         .endm
 484
 485
 486 /****************************************************************************/
 487 /*                                                                          */
 488 /* exception handlers                                                       */
 489 /*                                                                          */
 490 /****************************************************************************/
 491
 492         .align  5
 493 undefined_instruction:
 494         get_bad_stack
 495         bad_save_user_regs
 496         bl      do_undefined_instruction
 497
 498         .align  5
 499 software_interrupt:
 500         get_bad_stack
 501         bad_save_user_regs
 502         bl      do_software_interrupt
 503
 504         .align  5
 505 prefetch_abort:
 506         get_bad_stack
 507         bad_save_user_regs
 508         bl      do_prefetch_abort
 509
 510         .align  5
 511 data_abort:
 512         get_bad_stack
 513         bad_save_user_regs
 514         bl      do_data_abort
 515
 516         .align  5
 517 not_used:
 518         get_bad_stack
 519         bad_save_user_regs
 520         bl      do_not_used
 521
 522 #ifdef CONFIG_USE_IRQ
 523
 524         .align  5
 525 irq:
 526         get_irq_stack
 527         irq_save_user_regs
 528         bl      do_irq
 529         irq_restore_user_regs
 530
 531         .align  5
 532 fiq:
 533         get_fiq_stack
 534         irq_save_user_regs              /* someone ought to write a more    */
 535         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 536         irq_restore_user_regs
 537
 538 #else
 539
 540         .align  5
 541 irq:
 542         get_bad_stack
 543         bad_save_user_regs
 544         bl      do_irq
 545
 546         .align  5
 547 fiq:
 548         get_bad_stack
 549         bad_save_user_regs
 550         bl      do_fiq
 551
 552 #endif
 553
 554 /****************************************************************************/
 555 /*                                                                          */
 556 /* Reset function: Use Watchdog to reset                                    */
 557 /*                                                                          */
 558 /****************************************************************************/
 559
 560         .align  5
 561 .globl reset_cpu
 562
 563 reset_cpu:
 564         ldr     r1, =0x482e
 565         ldr     r2, =IXP425_OSWK
 566         str     r1, [r2]
 567         ldr     r1, =0x0fff
 568         ldr     r2, =IXP425_OSWT
 569         str     r1, [r2]
 570         ldr     r1, =0x5
 571         ldr     r2, =IXP425_OSWE
 572         str     r1, [r2]
 573         b       reset_endless
 574
 575
 576 reset_endless:
 577
 578         b       reset_endless
 579
 580 #ifdef CONFIG_USE_IRQ
 581
 582 .LC0:           .word   loops_per_jiffy
 583
 584 /*
 585  * 0 <= r0 <= 2000
 586  */
 587 .globl __udelay
 588 __udelay:
 589         mov     r2,     #0x6800
 590         orr     r2, r2, #0x00db
 591         mul     r0, r2, r0
 592         ldr     r2, .LC0
 593         ldr     r2, [r2]                @ max = 0x0fffffff
 594         mov     r0, r0, lsr #11         @ max = 0x00003fff
 595         mov     r2, r2, lsr #11         @ max = 0x0003ffff
 596         mul     r0, r2, r0              @ max = 2^32-1
 597         movs    r0, r0, lsr #6
 598
 599 delay_loop:
 600         subs    r0, r0, #1
 601         bne     delay_loop
 602         mov     pc, lr
 603
 604 #endif /* CONFIG_USE_IRQ */