arch/arm/cpu/lh7a40x/start.S

   1 /*
   2  *  armboot - Startup Code for ARM920 CPU-core
   3  *
   4  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   5  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
   6  *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <asm-offsets.h>
  28 #include <config.h>
  29 #include <version.h>
  30
  31 /*
  32  *************************************************************************
  33  *
  34  * Jump vector table as in table 3.1 in [1]
  35  *
  36  *************************************************************************
  37  */
  38
  39
  40 .globl _start
  41 _start: b       reset
  42         ldr     pc, _undefined_instruction
  43         ldr     pc, _software_interrupt
  44         ldr     pc, _prefetch_abort
  45         ldr     pc, _data_abort
  46         ldr     pc, _not_used
  47         ldr     pc, _irq
  48         ldr     pc, _fiq
  49
  50 _undefined_instruction: .word undefined_instruction
  51 _software_interrupt:    .word software_interrupt
  52 _prefetch_abort:        .word prefetch_abort
  53 _data_abort:            .word data_abort
  54 _not_used:              .word not_used
  55 _irq:                   .word irq
  56 _fiq:                   .word fiq
  57
  58         .balignl 16,0xdeadbeef
  59
  60
  61 /*
  62  *************************************************************************
  63  *
  64  * Startup Code (reset vector)
  65  *
  66  * do important init only if we don't start from memory!
  67  * relocate armboot to ram
  68  * setup stack
  69  * jump to second stage
  70  *
  71  *************************************************************************
  72  */
  73
  74 .globl _TEXT_BASE
  75 _TEXT_BASE:
  76         .word   CONFIG_SYS_TEXT_BASE
  77
  78 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  79 .globl _armboot_start
  80 _armboot_start:
  81         .word _start
  82 #endif
  83
  84 /*
  85  * These are defined in the board-specific linker script.
  86  */
  87 .globl _bss_start
  88 _bss_start:
  89         .word __bss_start
  90
  91 .globl _bss_end
  92 _bss_end:
  93         .word _end
  94
  95 #ifdef CONFIG_USE_IRQ
  96 /* IRQ stack memory (calculated at run-time) */
  97 .globl IRQ_STACK_START
  98 IRQ_STACK_START:
  99         .word   0x0badc0de
 100
 101 /* IRQ stack memory (calculated at run-time) */
 102 .globl FIQ_STACK_START
 103 FIQ_STACK_START:
 104         .word 0x0badc0de
 105 #endif
 106
 107 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 108 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 109 .globl IRQ_STACK_START_IN
 110 IRQ_STACK_START_IN:
 111         .word   0x0badc0de
 112
 113 .globl _datarel_start
 114 _datarel_start:
 115         .word __datarel_start
 116
 117 .globl _datarelrolocal_start
 118 _datarelrolocal_start:
 119         .word __datarelrolocal_start
 120
 121 .globl _datarellocal_start
 122 _datarellocal_start:
 123         .word __datarellocal_start
 124
 125 .globl _datarelro_start
 126 _datarelro_start:
 127         .word __datarelro_start
 128
 129 .globl _got_start
 130 _got_start:
 131         .word __got_start
 132
 133 .globl _got_end
 134 _got_end:
 135         .word __got_end
 136
 137 /*
 138  * the actual reset code
 139  */
 140
 141 reset:
 142         /*
 143          * set the cpu to SVC32 mode
 144          */
 145         mrs     r0,cpsr
 146         bic     r0,r0,#0x1f
 147         orr     r0,r0,#0xd3
 148         msr     cpsr,r0
 149
 150 #define pWDTCTL         0x80001400  /* Watchdog Timer control register */
 151 #define pINTENC         0x8000050C  /* Interupt-Controller enable clear register */
 152 #define pCLKSET         0x80000420  /* clock divisor register */
 153
 154         /* disable watchdog, set watchdog control register to
 155          * all zeros (default reset)
 156          */
 157         ldr     r0, =pWDTCTL
 158         mov     r1, #0x0
 159         str     r1, [r0]
 160
 161         /*
 162          * mask all IRQs by setting all bits in the INTENC register (default)
 163          */
 164         mov     r1, #0xffffffff
 165         ldr     r0, =pINTENC
 166         str     r1, [r0]
 167
 168         /* FCLK:HCLK:PCLK = 1:2:2 */
 169         /* default FCLK is 200 MHz, using 14.7456 MHz fin */
 170         ldr     r0, =pCLKSET
 171         ldr r1, =0x0004ee39
 172 @       ldr r1, =0x0005ee39     @ 1: 2: 4
 173         str     r1, [r0]
 174
 175         /*
 176          * we do sys-critical inits only at reboot,
 177          * not when booting from ram!
 178          */
 179 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 180         bl      cpu_init_crit
 181 #endif
 182
 183 /* Set stackpointer in internal RAM to call board_init_f */
 184 call_board_init_f:
 185         ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 186         ldr     r0,=0x00000000
 187         bl      board_init_f
 188
 189 /*------------------------------------------------------------------------------*/
 190
 191 /*
 192  * void relocate_code (addr_sp, gd, addr_moni)
 193  *
 194  * This "function" does not return, instead it continues in RAM
 195  * after relocating the monitor code.
 196  *
 197  */
 198         .globl  relocate_code
 199 relocate_code:
 200         mov     r4, r0  /* save addr_sp */
 201         mov     r5, r1  /* save addr of gd */
 202         mov     r6, r2  /* save addr of destination */
 203         mov     r7, r2  /* save addr of destination */
 204
 205         /* Set up the stack                                                 */
 206 stack_setup:
 207         mov     sp, r4
 208
 209         adr     r0, _start
 210         ldr     r2, _TEXT_BASE
 211         ldr     r3, _bss_start
 212         sub     r2, r3, r2              /* r2 <- size of armboot            */
 213         add     r2, r0, r2              /* r2 <- source end address         */
 214         cmp     r0, r6
 215         beq     clear_bss
 216
 217 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 218 copy_loop:
 219         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 220         stmia   r6!, {r9-r10}           /* copy to   target address [r1]    */
 221         cmp     r0, r2                  /* until source end address [r2]    */
 222         blo     copy_loop
 223
 224 #ifndef CONFIG_PRELOADER
 225         /* fix got entries */
 226         ldr     r1, _TEXT_BASE          /* Text base */
 227         mov     r0, r7                  /* reloc addr */
 228         ldr     r2, _got_start          /* addr in Flash */
 229         ldr     r3, _got_end            /* addr in Flash */
 230         sub     r3, r3, r1
 231         add     r3, r3, r0
 232         sub     r2, r2, r1
 233         add     r2, r2, r0
 234
 235 fixloop:
 236         ldr     r4, [r2]
 237         sub     r4, r4, r1
 238         add     r4, r4, r0
 239         str     r4, [r2]
 240         add     r2, r2, #4
 241         cmp     r2, r3
 242         blo     fixloop
 243 #endif
 244 #endif  /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 245
 246 clear_bss:
 247 #ifndef CONFIG_PRELOADER
 248         ldr     r0, _bss_start
 249         ldr     r1, _bss_end
 250         ldr     r3, _TEXT_BASE          /* Text base */
 251         mov     r4, r7                  /* reloc addr */
 252         sub     r0, r0, r3
 253         add     r0, r0, r4
 254         sub     r1, r1, r3
 255         add     r1, r1, r4
 256         mov     r2, #0x00000000         /* clear                            */
 257
 258 clbss_l:str     r2, [r0]                /* clear loop...                    */
 259         add     r0, r0, #4
 260         cmp     r0, r1
 261         bne     clbss_l
 262 #endif
 263
 264 /*
 265  * We are done. Do not return, instead branch to second part of board
 266  * initialization, now running from RAM.
 267  */
 268         ldr     r0, _TEXT_BASE
 269         ldr     r2, _board_init_r
 270         sub     r2, r2, r0
 271         add     r2, r2, r7      /* position from board_init_r in RAM */
 272         /* setup parameters for board_init_r */
 273         mov     r0, r5          /* gd_t */
 274         mov     r1, r7          /* dest_addr */
 275         /* jump to it ... */
 276         mov     lr, r2
 277         mov     pc, lr
 278
 279 _board_init_r: .word board_init_r
 280
 281 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
 282 /*
 283  * the actual reset code
 284  */
 285
 286 reset:
 287         /*
 288          * set the cpu to SVC32 mode
 289          */
 290         mrs     r0,cpsr
 291         bic     r0,r0,#0x1f
 292         orr     r0,r0,#0xd3
 293         msr     cpsr,r0
 294
 295 #define pWDTCTL         0x80001400  /* Watchdog Timer control register */
 296 #define pINTENC         0x8000050C  /* Interupt-Controller enable clear register */
 297 #define pCLKSET         0x80000420  /* clock divisor register */
 298
 299         /* disable watchdog, set watchdog control register to
 300          * all zeros (default reset)
 301          */
 302         ldr     r0, =pWDTCTL
 303         mov     r1, #0x0
 304         str     r1, [r0]
 305
 306         /*
 307          * mask all IRQs by setting all bits in the INTENC register (default)
 308          */
 309         mov     r1, #0xffffffff
 310         ldr     r0, =pINTENC
 311         str     r1, [r0]
 312
 313         /* FCLK:HCLK:PCLK = 1:2:2 */
 314         /* default FCLK is 200 MHz, using 14.7456 MHz fin */
 315         ldr     r0, =pCLKSET
 316         ldr r1, =0x0004ee39
 317 @       ldr r1, =0x0005ee39     @ 1: 2: 4
 318         str     r1, [r0]
 319
 320         /*
 321          * we do sys-critical inits only at reboot,
 322          * not when booting from ram!
 323          */
 324 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 325         bl      cpu_init_crit
 326 #endif
 327
 328 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 329 relocate:                               /* relocate U-Boot to RAM           */
 330         adr     r0, _start              /* r0 <- current position of code   */
 331         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 332         cmp     r0, r1                  /* don't reloc during debug         */
 333         beq     stack_setup
 334
 335         ldr     r2, _armboot_start
 336         ldr     r3, _bss_start
 337         sub     r2, r3, r2              /* r2 <- size of armboot            */
 338         add     r2, r0, r2              /* r2 <- source end address         */
 339
 340 copy_loop:
 341         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 342         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 343         cmp     r0, r2                  /* until source end address [r2]    */
 344         blo     copy_loop
 345 #endif  /* CONFIG_SKIP_RELOCATE_UBOOT */
 346
 347         /* Set up the stack                                                 */
 348 stack_setup:
 349         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 350         sub     r0, r0, #CONFIG_SYS_MALLOC_LEN  /* malloc area                      */
 351         sub     r0, r0, #GENERATED_GBL_DATA_SIZE /* bdinfo                        */
 352 #ifdef CONFIG_USE_IRQ
 353         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 354 #endif
 355         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 356         bic     sp, sp, #7              /* 8-byte alignment for ABI compliance */
 357
 358 clear_bss:
 359         ldr     r0, _bss_start          /* find start of bss segment        */
 360         @add    r0, r0, #4              /* start at first byte of bss       */
 361                                         /*   why inc. 4 bytes past then?    */
 362         ldr     r1, _bss_end            /* stop here                        */
 363         mov     r2, #0x00000000         /* clear                            */
 364
 365 clbss_l:str     r2, [r0]                /* clear loop...                    */
 366         add     r0, r0, #4
 367         cmp     r0, r1
 368         blo     clbss_l
 369
 370         ldr     pc, _start_armboot
 371
 372 _start_armboot: .word start_armboot
 373 #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
 374
 375 /*
 376  *************************************************************************
 377  *
 378  * CPU_init_critical registers
 379  *
 380  * setup important registers
 381  * setup memory timing
 382  *
 383  *************************************************************************
 384  */
 385
 386
 387 cpu_init_crit:
 388         /*
 389          * flush v4 I/D caches
 390          */
 391         mov     r0, #0
 392         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 393         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 394
 395         /*
 396          * disable MMU stuff and caches
 397          */
 398         mrc     p15, 0, r0, c1, c0, 0
 399         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 400         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 401         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 402         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 403         orr     r0, r0, #0x40000000     @ set bit 30 (nF) notFastBus
 404         mcr     p15, 0, r0, c1, c0, 0
 405
 406
 407         /*
 408          * before relocating, we have to setup RAM timing
 409          * because memory timing is board-dependend, you will
 410          * find a lowlevel_init.S in your board directory.
 411          */
 412         mov     ip, lr
 413         bl      lowlevel_init
 414         mov     lr, ip
 415
 416         mov     pc, lr
 417
 418
 419 /*
 420  *************************************************************************
 421  *
 422  * Interrupt handling
 423  *
 424  *************************************************************************
 425  */
 426
 427 @
 428 @ IRQ stack frame.
 429 @
 430 #define S_FRAME_SIZE    72
 431
 432 #define S_OLD_R0        68
 433 #define S_PSR           64
 434 #define S_PC            60
 435 #define S_LR            56
 436 #define S_SP            52
 437
 438 #define S_IP            48
 439 #define S_FP            44
 440 #define S_R10           40
 441 #define S_R9            36
 442 #define S_R8            32
 443 #define S_R7            28
 444 #define S_R6            24
 445 #define S_R5            20
 446 #define S_R4            16
 447 #define S_R3            12
 448 #define S_R2            8
 449 #define S_R1            4
 450 #define S_R0            0
 451
 452 #define MODE_SVC 0x13
 453 #define I_BIT    0x80
 454
 455 /*
 456  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 457  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 458  */
 459
 460         .macro  bad_save_user_regs
 461         sub     sp, sp, #S_FRAME_SIZE
 462         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 463 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 464         ldr     r2, _armboot_start
 465         sub     r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
 466         sub     r2, r2, #(GENERATED_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 467 #else
 468         ldr     r2, IRQ_STACK_START_IN
 469 #endif
 470         ldmia   r2, {r2 - r3}                   @ get pc, cpsr
 471         add     r0, sp, #S_FRAME_SIZE           @ restore sp_SVC
 472
 473         add     r5, sp, #S_SP
 474         mov     r1, lr
 475         stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 476         mov     r0, sp
 477         .endm
 478
 479         .macro  irq_save_user_regs
 480         sub     sp, sp, #S_FRAME_SIZE
 481         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 482         add     r8, sp, #S_PC
 483         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 484         str     lr, [r8, #0]                    @ Save calling PC
 485         mrs     r6, spsr
 486         str     r6, [r8, #4]                    @ Save CPSR
 487         str     r0, [r8, #8]                    @ Save OLD_R0
 488         mov     r0, sp
 489         .endm
 490
 491         .macro  irq_restore_user_regs
 492         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 493         mov     r0, r0
 494         ldr     lr, [sp, #S_PC]                 @ Get PC
 495         add     sp, sp, #S_FRAME_SIZE
 496         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 497         .endm
 498
 499         .macro get_bad_stack
 500 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 501         ldr     r13, _armboot_start             @ setup our mode stack
 502         sub     r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
 503         sub     r13, r13, #(GENERATED_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 504 #else
 505         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 506 #endif
 507
 508         str     lr, [r13]                       @ save caller lr / spsr
 509         mrs     lr, spsr
 510         str     lr, [r13, #4]
 511
 512         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 513         @ msr   spsr_c, r13
 514         msr     spsr, r13
 515         mov     lr, pc
 516         movs    pc, lr
 517         .endm
 518
 519         .macro get_irq_stack                    @ setup IRQ stack
 520         ldr     sp, IRQ_STACK_START
 521         .endm
 522
 523         .macro get_fiq_stack                    @ setup FIQ stack
 524         ldr     sp, FIQ_STACK_START
 525         .endm
 526
 527 /*
 528  * exception handlers
 529  */
 530         .align  5
 531 undefined_instruction:
 532         get_bad_stack
 533         bad_save_user_regs
 534         bl      do_undefined_instruction
 535
 536         .align  5
 537 software_interrupt:
 538         get_bad_stack
 539         bad_save_user_regs
 540         bl      do_software_interrupt
 541
 542         .align  5
 543 prefetch_abort:
 544         get_bad_stack
 545         bad_save_user_regs
 546         bl      do_prefetch_abort
 547
 548         .align  5
 549 data_abort:
 550         get_bad_stack
 551         bad_save_user_regs
 552         bl      do_data_abort
 553
 554         .align  5
 555 not_used:
 556         get_bad_stack
 557         bad_save_user_regs
 558         bl      do_not_used
 559
 560 #ifdef CONFIG_USE_IRQ
 561
 562         .align  5
 563 irq:
 564         get_irq_stack
 565         irq_save_user_regs
 566         bl      do_irq
 567         irq_restore_user_regs
 568
 569         .align  5
 570 fiq:
 571         get_fiq_stack
 572         /* someone ought to write a more effiction fiq_save_user_regs */
 573         irq_save_user_regs
 574         bl      do_fiq
 575         irq_restore_user_regs
 576
 577 #else
 578
 579         .align  5
 580 irq:
 581         get_bad_stack
 582         bad_save_user_regs
 583         bl      do_irq
 584
 585         .align  5
 586 fiq:
 587         get_bad_stack
 588         bad_save_user_regs
 589         bl      do_fiq
 590
 591 #endif
 592
 593         .align  5
 594 .globl reset_cpu
 595 reset_cpu:
 596         bl      disable_interrupts
 597
 598         /* Disable watchdog */
 599         ldr     r1, =pWDTCTL
 600         mov     r3, #0
 601         str     r3, [r1]
 602
 603         /* reset counter */
 604         ldr     r3, =0x00001984
 605         str     r3, [r1, #4]
 606
 607         /* Enable the watchdog */
 608         mov     r3, #1
 609         str     r3, [r1]
 610
 611 _loop_forever:
 612         b       _loop_forever