arch/arm/cpu/lh7a40x/start.S

   1 /*
   2  *  armboot - Startup Code for ARM920 CPU-core
   3  *
   4  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   5  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
   6  *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <asm-offsets.h>
  28 #include <config.h>
  29 #include <version.h>
  30
  31 /*
  32  *************************************************************************
  33  *
  34  * Jump vector table as in table 3.1 in [1]
  35  *
  36  *************************************************************************
  37  */
  38
  39
  40 .globl _start
  41 _start: b       reset
  42         ldr     pc, _undefined_instruction
  43         ldr     pc, _software_interrupt
  44         ldr     pc, _prefetch_abort
  45         ldr     pc, _data_abort
  46         ldr     pc, _not_used
  47         ldr     pc, _irq
  48         ldr     pc, _fiq
  49
  50 _undefined_instruction: .word undefined_instruction
  51 _software_interrupt:    .word software_interrupt
  52 _prefetch_abort:        .word prefetch_abort
  53 _data_abort:            .word data_abort
  54 _not_used:              .word not_used
  55 _irq:                   .word irq
  56 _fiq:                   .word fiq
  57
  58         .balignl 16,0xdeadbeef
  59
  60
  61 /*
  62  *************************************************************************
  63  *
  64  * Startup Code (reset vector)
  65  *
  66  * do important init only if we don't start from memory!
  67  * relocate armboot to ram
  68  * setup stack
  69  * jump to second stage
  70  *
  71  *************************************************************************
  72  */
  73
  74 .globl _TEXT_BASE
  75 _TEXT_BASE:
  76         .word   CONFIG_SYS_TEXT_BASE
  77
  78 /*
  79  * These are defined in the board-specific linker script.
  80  * Subtracting _start from them lets the linker put their
  81  * relative position in the executable instead of leaving
  82  * them null.
  83  */
  84 .globl _bss_start_ofs
  85 _bss_start_ofs:
  86         .word __bss_start - _start
  87
  88 .globl _bss_end_ofs
  89 _bss_end_ofs:
  90         .word __bss_end__ - _start
  91
  92 .globl _end_ofs
  93 _end_ofs:
  94         .word _end - _start
  95
  96 #ifdef CONFIG_USE_IRQ
  97 /* IRQ stack memory (calculated at run-time) */
  98 .globl IRQ_STACK_START
  99 IRQ_STACK_START:
 100         .word   0x0badc0de
 101
 102 /* IRQ stack memory (calculated at run-time) */
 103 .globl FIQ_STACK_START
 104 FIQ_STACK_START:
 105         .word 0x0badc0de
 106 #endif
 107
 108 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 109 .globl IRQ_STACK_START_IN
 110 IRQ_STACK_START_IN:
 111         .word   0x0badc0de
 112
 113 /*
 114  * the actual reset code
 115  */
 116
 117 reset:
 118         /*
 119          * set the cpu to SVC32 mode
 120          */
 121         mrs     r0,cpsr
 122         bic     r0,r0,#0x1f
 123         orr     r0,r0,#0xd3
 124         msr     cpsr,r0
 125
 126 #define pWDTCTL         0x80001400  /* Watchdog Timer control register */
 127 #define pINTENC         0x8000050C  /* Interupt-Controller enable clear register */
 128 #define pCLKSET         0x80000420  /* clock divisor register */
 129
 130         /* disable watchdog, set watchdog control register to
 131          * all zeros (default reset)
 132          */
 133         ldr     r0, =pWDTCTL
 134         mov     r1, #0x0
 135         str     r1, [r0]
 136
 137         /*
 138          * mask all IRQs by setting all bits in the INTENC register (default)
 139          */
 140         mov     r1, #0xffffffff
 141         ldr     r0, =pINTENC
 142         str     r1, [r0]
 143
 144         /* FCLK:HCLK:PCLK = 1:2:2 */
 145         /* default FCLK is 200 MHz, using 14.7456 MHz fin */
 146         ldr     r0, =pCLKSET
 147         ldr r1, =0x0004ee39
 148 @       ldr r1, =0x0005ee39     @ 1: 2: 4
 149         str     r1, [r0]
 150
 151         /*
 152          * we do sys-critical inits only at reboot,
 153          * not when booting from ram!
 154          */
 155 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 156         bl      cpu_init_crit
 157 #endif
 158
 159 /* Set stackpointer in internal RAM to call board_init_f */
 160 call_board_init_f:
 161         ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 162         bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
 163         ldr     r0,=0x00000000
 164         bl      board_init_f
 165
 166 /*------------------------------------------------------------------------------*/
 167
 168 /*
 169  * void relocate_code (addr_sp, gd, addr_moni)
 170  *
 171  * This "function" does not return, instead it continues in RAM
 172  * after relocating the monitor code.
 173  *
 174  */
 175         .globl  relocate_code
 176 relocate_code:
 177         mov     r4, r0  /* save addr_sp */
 178         mov     r5, r1  /* save addr of gd */
 179         mov     r6, r2  /* save addr of destination */
 180
 181         /* Set up the stack                                                 */
 182 stack_setup:
 183         mov     sp, r4
 184
 185         adr     r0, _start
 186         cmp     r0, r6
 187         beq     clear_bss               /* skip relocation */
 188         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 189         ldr     r3, _bss_start_ofs
 190         add     r2, r0, r3              /* r2 <- source end address         */
 191
 192 copy_loop:
 193         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 194         stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 195         cmp     r0, r2                  /* until source end address [r2]    */
 196         blo     copy_loop
 197
 198 #ifndef CONFIG_SPL_BUILD
 199         /*
 200          * fix .rel.dyn relocations
 201          */
 202         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 203         sub     r9, r6, r0              /* r9 <- relocation offset */
 204         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 205         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 206         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 207         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 208         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 209         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 210 fixloop:
 211         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 212         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 213         ldr     r1, [r2, #4]
 214         and     r7, r1, #0xff
 215         cmp     r7, #23                 /* relative fixup? */
 216         beq     fixrel
 217         cmp     r7, #2                  /* absolute fixup? */
 218         beq     fixabs
 219         /* ignore unknown type of fixup */
 220         b       fixnext
 221 fixabs:
 222         /* absolute fix: set location to (offset) symbol value */
 223         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 224         add     r1, r10, r1             /* r1 <- address of symbol in table */
 225         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 226         add     r1, r1, r9              /* r1 <- relocated sym addr */
 227         b       fixnext
 228 fixrel:
 229         /* relative fix: increase location by offset */
 230         ldr     r1, [r0]
 231         add     r1, r1, r9
 232 fixnext:
 233         str     r1, [r0]
 234         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 235         cmp     r2, r3
 236         blo     fixloop
 237 #endif
 238
 239 clear_bss:
 240 #ifndef CONFIG_SPL_BUILD
 241         ldr     r0, _bss_start_ofs
 242         ldr     r1, _bss_end_ofs
 243         mov     r4, r6                  /* reloc addr */
 244         add     r0, r0, r4
 245         add     r1, r1, r4
 246         mov     r2, #0x00000000         /* clear                            */
 247
 248 clbss_l:str     r2, [r0]                /* clear loop...                    */
 249         add     r0, r0, #4
 250         cmp     r0, r1
 251         bne     clbss_l
 252 #endif
 253
 254 /*
 255  * We are done. Do not return, instead branch to second part of board
 256  * initialization, now running from RAM.
 257  */
 258         ldr     r0, _board_init_r_ofs
 259         adr     r1, _start
 260         add     lr, r0, r1
 261         add     lr, lr, r9
 262         /* setup parameters for board_init_r */
 263         mov     r0, r5          /* gd_t */
 264         mov     r1, r6          /* dest_addr */
 265         /* jump to it ... */
 266         mov     pc, lr
 267
 268 _board_init_r_ofs:
 269         .word board_init_r - _start
 270
 271 _rel_dyn_start_ofs:
 272         .word __rel_dyn_start - _start
 273 _rel_dyn_end_ofs:
 274         .word __rel_dyn_end - _start
 275 _dynsym_start_ofs:
 276         .word __dynsym_start - _start
 277
 278 /*
 279  *************************************************************************
 280  *
 281  * CPU_init_critical registers
 282  *
 283  * setup important registers
 284  * setup memory timing
 285  *
 286  *************************************************************************
 287  */
 288
 289
 290 cpu_init_crit:
 291         /*
 292          * flush v4 I/D caches
 293          */
 294         mov     r0, #0
 295         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 296         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 297
 298         /*
 299          * disable MMU stuff and caches
 300          */
 301         mrc     p15, 0, r0, c1, c0, 0
 302         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 303         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 304         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 305         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 306         orr     r0, r0, #0x40000000     @ set bit 30 (nF) notFastBus
 307         mcr     p15, 0, r0, c1, c0, 0
 308
 309
 310         /*
 311          * before relocating, we have to setup RAM timing
 312          * because memory timing is board-dependend, you will
 313          * find a lowlevel_init.S in your board directory.
 314          */
 315         mov     ip, lr
 316         bl      lowlevel_init
 317         mov     lr, ip
 318
 319         mov     pc, lr
 320
 321
 322 /*
 323  *************************************************************************
 324  *
 325  * Interrupt handling
 326  *
 327  *************************************************************************
 328  */
 329
 330 @
 331 @ IRQ stack frame.
 332 @
 333 #define S_FRAME_SIZE    72
 334
 335 #define S_OLD_R0        68
 336 #define S_PSR           64
 337 #define S_PC            60
 338 #define S_LR            56
 339 #define S_SP            52
 340
 341 #define S_IP            48
 342 #define S_FP            44
 343 #define S_R10           40
 344 #define S_R9            36
 345 #define S_R8            32
 346 #define S_R7            28
 347 #define S_R6            24
 348 #define S_R5            20
 349 #define S_R4            16
 350 #define S_R3            12
 351 #define S_R2            8
 352 #define S_R1            4
 353 #define S_R0            0
 354
 355 #define MODE_SVC 0x13
 356 #define I_BIT    0x80
 357
 358 /*
 359  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 360  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 361  */
 362
 363         .macro  bad_save_user_regs
 364         sub     sp, sp, #S_FRAME_SIZE
 365         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 366         ldr     r2, IRQ_STACK_START_IN
 367         ldmia   r2, {r2 - r3}                   @ get pc, cpsr
 368         add     r0, sp, #S_FRAME_SIZE           @ restore sp_SVC
 369
 370         add     r5, sp, #S_SP
 371         mov     r1, lr
 372         stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 373         mov     r0, sp
 374         .endm
 375
 376         .macro  irq_save_user_regs
 377         sub     sp, sp, #S_FRAME_SIZE
 378         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 379         add     r8, sp, #S_PC
 380         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 381         str     lr, [r8, #0]                    @ Save calling PC
 382         mrs     r6, spsr
 383         str     r6, [r8, #4]                    @ Save CPSR
 384         str     r0, [r8, #8]                    @ Save OLD_R0
 385         mov     r0, sp
 386         .endm
 387
 388         .macro  irq_restore_user_regs
 389         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 390         mov     r0, r0
 391         ldr     lr, [sp, #S_PC]                 @ Get PC
 392         add     sp, sp, #S_FRAME_SIZE
 393         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 394         .endm
 395
 396         .macro get_bad_stack
 397         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 398
 399         str     lr, [r13]                       @ save caller lr / spsr
 400         mrs     lr, spsr
 401         str     lr, [r13, #4]
 402
 403         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 404         @ msr   spsr_c, r13
 405         msr     spsr, r13
 406         mov     lr, pc
 407         movs    pc, lr
 408         .endm
 409
 410         .macro get_irq_stack                    @ setup IRQ stack
 411         ldr     sp, IRQ_STACK_START
 412         .endm
 413
 414         .macro get_fiq_stack                    @ setup FIQ stack
 415         ldr     sp, FIQ_STACK_START
 416         .endm
 417
 418 /*
 419  * exception handlers
 420  */
 421         .align  5
 422 undefined_instruction:
 423         get_bad_stack
 424         bad_save_user_regs
 425         bl      do_undefined_instruction
 426
 427         .align  5
 428 software_interrupt:
 429         get_bad_stack
 430         bad_save_user_regs
 431         bl      do_software_interrupt
 432
 433         .align  5
 434 prefetch_abort:
 435         get_bad_stack
 436         bad_save_user_regs
 437         bl      do_prefetch_abort
 438
 439         .align  5
 440 data_abort:
 441         get_bad_stack
 442         bad_save_user_regs
 443         bl      do_data_abort
 444
 445         .align  5
 446 not_used:
 447         get_bad_stack
 448         bad_save_user_regs
 449         bl      do_not_used
 450
 451 #ifdef CONFIG_USE_IRQ
 452
 453         .align  5
 454 irq:
 455         get_irq_stack
 456         irq_save_user_regs
 457         bl      do_irq
 458         irq_restore_user_regs
 459
 460         .align  5
 461 fiq:
 462         get_fiq_stack
 463         /* someone ought to write a more effiction fiq_save_user_regs */
 464         irq_save_user_regs
 465         bl      do_fiq
 466         irq_restore_user_regs
 467
 468 #else
 469
 470         .align  5
 471 irq:
 472         get_bad_stack
 473         bad_save_user_regs
 474         bl      do_irq
 475
 476         .align  5
 477 fiq:
 478         get_bad_stack
 479         bad_save_user_regs
 480         bl      do_fiq
 481
 482 #endif
 483
 484         .align  5
 485 .globl reset_cpu
 486 reset_cpu:
 487         bl      disable_interrupts
 488
 489         /* Disable watchdog */
 490         ldr     r1, =pWDTCTL
 491         mov     r3, #0
 492         str     r3, [r1]
 493
 494         /* reset counter */
 495         ldr     r3, =0x00001984
 496         str     r3, [r1, #4]
 497
 498         /* Enable the watchdog */
 499         mov     r3, #1
 500         str     r3, [r1]
 501
 502 _loop_forever:
 503         b       _loop_forever