arch/arm/cpu/s3c44b0/start.S

   1 /*
   2  * Startup Code for S3C44B0 CPU-core
   3  *
   4  * (C) Copyright 2004
   5  * DAVE Srl
   6  *
   7  * http://www.dave-tech.it
   8  * http://www.wawnet.biz
   9  * mailto:info@wawnet.biz
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <asm-offsets.h>
  15 #include <config.h>
  16 #include <version.h>
  17
  18 /*
  19  * Jump vector table
  20  */
  21
  22
  23 .globl _start
  24 _start: b       reset
  25         add     pc, pc, #0x0c000000
  26         add     pc, pc, #0x0c000000
  27         add     pc, pc, #0x0c000000
  28         add     pc, pc, #0x0c000000
  29         add     pc, pc, #0x0c000000
  30         add     pc, pc, #0x0c000000
  31         add     pc, pc, #0x0c000000
  32
  33         .balignl 16,0xdeadbeef
  34
  35
  36 /*
  37  *************************************************************************
  38  *
  39  * Startup Code (reset vector)
  40  *
  41  * do important init only if we don't start from memory!
  42  * relocate u-boot to ram
  43  * setup stack
  44  * jump to second stage
  45  *
  46  *************************************************************************
  47  */
  48
  49 .globl _TEXT_BASE
  50 _TEXT_BASE:
  51 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  52         .word   CONFIG_SPL_TEXT_BASE
  53 #else
  54         .word   CONFIG_SYS_TEXT_BASE
  55 #endif
  56
  57 /*
  58  * These are defined in the board-specific linker script.
  59  * Subtracting _start from them lets the linker put their
  60  * relative position in the executable instead of leaving
  61  * them null.
  62  */
  63 .globl _bss_start_ofs
  64 _bss_start_ofs:
  65         .word __bss_start - _start
  66
  67 .globl _bss_end_ofs
  68 _bss_end_ofs:
  69         .word __bss_end - _start
  70
  71 .globl _end_ofs
  72 _end_ofs:
  73         .word _end - _start
  74
  75 #ifdef CONFIG_USE_IRQ
  76 /* IRQ stack memory (calculated at run-time) */
  77 .globl IRQ_STACK_START
  78 IRQ_STACK_START:
  79         .word   0x0badc0de
  80
  81 /* IRQ stack memory (calculated at run-time) */
  82 .globl FIQ_STACK_START
  83 FIQ_STACK_START:
  84         .word 0x0badc0de
  85 #endif
  86
  87 /* IRQ stack memory (calculated at run-time) + 8 bytes */
  88 .globl IRQ_STACK_START_IN
  89 IRQ_STACK_START_IN:
  90         .word   0x0badc0de
  91
  92 /*
  93  * the actual reset code
  94  */
  95
  96 reset:
  97         /*
  98          * set the cpu to SVC32 mode
  99          */
 100         mrs     r0,cpsr
 101         bic     r0,r0,#0x1f
 102         orr     r0,r0,#0xd3
 103         msr     cpsr,r0
 104
 105         /*
 106          * we do sys-critical inits only at reboot,
 107          * not when booting from ram!
 108          */
 109 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 110         bl      cpu_init_crit
 111         /*
 112          * before relocating, we have to setup RAM timing
 113          * because memory timing is board-dependend, you will
 114          * find a lowlevel_init.S in your board directory.
 115          */
 116         bl      lowlevel_init
 117 #endif
 118
 119         bl      _main
 120
 121 /*------------------------------------------------------------------------------*/
 122
 123         .globl  c_runtime_cpu_setup
 124 c_runtime_cpu_setup:
 125
 126         bx      lr
 127
 128 /*
 129  *************************************************************************
 130  *
 131  * CPU_init_critical registers
 132  *
 133  * setup important registers
 134  * setup memory timing
 135  *
 136  *************************************************************************
 137  */
 138
 139 #define INTCON (0x01c00000+0x200000)
 140 #define INTMSK (0x01c00000+0x20000c)
 141 #define LOCKTIME (0x01c00000+0x18000c)
 142 #define PLLCON (0x01c00000+0x180000)
 143 #define CLKCON (0x01c00000+0x180004)
 144 #define WTCON (0x01c00000+0x130000)
 145 cpu_init_crit:
 146         /* disable watch dog */
 147         ldr     r0, =WTCON
 148         ldr     r1, =0x0
 149         str     r1, [r0]
 150
 151         /*
 152          * mask all IRQs by clearing all bits in the INTMRs
 153          */
 154         ldr     r1,=INTMSK
 155         ldr     r0, =0x03fffeff
 156         str     r0, [r1]
 157
 158         ldr     r1, =INTCON
 159         ldr     r0, =0x05
 160         str     r0, [r1]
 161
 162         /* Set Clock Control Register */
 163         ldr     r1, =LOCKTIME
 164         ldrb    r0, =800
 165         strb    r0, [r1]
 166
 167         ldr     r1, =PLLCON
 168
 169 #if CONFIG_S3C44B0_CLOCK_SPEED==66
 170         ldr     r0, =0x34031    /* 66MHz (Quartz=11MHz) */
 171 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
 172         ldr     r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz  */
 173 #else
 174 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
 175 #endif
 176
 177         str     r0, [r1]
 178
 179         ldr     r1,=CLKCON
 180         ldr     r0, =0x7ff8
 181         str     r0, [r1]
 182
 183         mov     pc, lr
 184
 185
 186 /*************************************************/
 187 /*      interrupt vectors       */
 188 /*************************************************/
 189 real_vectors:
 190         b       reset
 191         b       undefined_instruction
 192         b       software_interrupt
 193         b       prefetch_abort
 194         b       data_abort
 195         b       not_used
 196         b       irq
 197         b       fiq
 198
 199 /*************************************************/
 200
 201 undefined_instruction:
 202         mov     r6, #3
 203         b       reset
 204
 205 software_interrupt:
 206         mov     r6, #4
 207         b       reset
 208
 209 prefetch_abort:
 210         mov     r6, #5
 211         b       reset
 212
 213 data_abort:
 214         mov     r6, #6
 215         b       reset
 216
 217 not_used:
 218         /* we *should* never reach this */
 219         mov     r6, #7
 220         b       reset
 221
 222 irq:
 223         mov     r6, #8
 224         b       reset
 225
 226 fiq:
 227         mov     r6, #9
 228         b       reset