arch/arm/cpu/s3c44b0/start.S

   1 /*
   2  * Startup Code for S3C44B0 CPU-core
   3  *
   4  * (C) Copyright 2004
   5  * DAVE Srl
   6  *
   7  * http://www.dave-tech.it
   8  * http://www.wawnet.biz
   9  * mailto:info@wawnet.biz
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <asm-offsets.h>
  31 #include <config.h>
  32 #include <version.h>
  33
  34 /*
  35  * Jump vector table
  36  */
  37
  38
  39 .globl _start
  40 _start: b       reset
  41         add     pc, pc, #0x0c000000
  42         add     pc, pc, #0x0c000000
  43         add     pc, pc, #0x0c000000
  44         add     pc, pc, #0x0c000000
  45         add     pc, pc, #0x0c000000
  46         add     pc, pc, #0x0c000000
  47         add     pc, pc, #0x0c000000
  48
  49         .balignl 16,0xdeadbeef
  50
  51
  52 /*
  53  *************************************************************************
  54  *
  55  * Startup Code (reset vector)
  56  *
  57  * do important init only if we don't start from memory!
  58  * relocate u-boot to ram
  59  * setup stack
  60  * jump to second stage
  61  *
  62  *************************************************************************
  63  */
  64
  65 .globl _TEXT_BASE
  66 _TEXT_BASE:
  67 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  68         .word   CONFIG_SPL_TEXT_BASE
  69 #else
  70         .word   CONFIG_SYS_TEXT_BASE
  71 #endif
  72
  73 /*
  74  * These are defined in the board-specific linker script.
  75  * Subtracting _start from them lets the linker put their
  76  * relative position in the executable instead of leaving
  77  * them null.
  78  */
  79 .globl _bss_start_ofs
  80 _bss_start_ofs:
  81         .word __bss_start - _start
  82
  83 .globl _bss_end_ofs
  84 _bss_end_ofs:
  85         .word __bss_end - _start
  86
  87 .globl _end_ofs
  88 _end_ofs:
  89         .word _end - _start
  90
  91 #ifdef CONFIG_USE_IRQ
  92 /* IRQ stack memory (calculated at run-time) */
  93 .globl IRQ_STACK_START
  94 IRQ_STACK_START:
  95         .word   0x0badc0de
  96
  97 /* IRQ stack memory (calculated at run-time) */
  98 .globl FIQ_STACK_START
  99 FIQ_STACK_START:
 100         .word 0x0badc0de
 101 #endif
 102
 103 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 104 .globl IRQ_STACK_START_IN
 105 IRQ_STACK_START_IN:
 106         .word   0x0badc0de
 107
 108 /*
 109  * the actual reset code
 110  */
 111
 112 reset:
 113         /*
 114          * set the cpu to SVC32 mode
 115          */
 116         mrs     r0,cpsr
 117         bic     r0,r0,#0x1f
 118         orr     r0,r0,#0xd3
 119         msr     cpsr,r0
 120
 121         /*
 122          * we do sys-critical inits only at reboot,
 123          * not when booting from ram!
 124          */
 125 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 126         bl      cpu_init_crit
 127         /*
 128          * before relocating, we have to setup RAM timing
 129          * because memory timing is board-dependend, you will
 130          * find a lowlevel_init.S in your board directory.
 131          */
 132         bl      lowlevel_init
 133 #endif
 134
 135         bl      _main
 136
 137 /*------------------------------------------------------------------------------*/
 138
 139 /*
 140  * void relocate_code (addr_sp, gd, addr_moni)
 141  *
 142  * This "function" does not return, instead it continues in RAM
 143  * after relocating the monitor code.
 144  *
 145  */
 146         .globl  relocate_code
 147 relocate_code:
 148         mov     r4, r0  /* save addr_sp */
 149         mov     r5, r1  /* save addr of gd */
 150         mov     r6, r2  /* save addr of destination */
 151
 152         adr     r0, _start
 153         cmp     r0, r6
 154         moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
 155         beq     relocate_done           /* skip relocation */
 156         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 157         ldr     r3, _bss_start_ofs
 158         add     r2, r0, r3              /* r2 <- source end address         */
 159
 160 copy_loop:
 161         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 162         stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 163         cmp     r0, r2                  /* until source end address [r2]    */
 164         blo     copy_loop
 165
 166 #ifndef CONFIG_SPL_BUILD
 167         /*
 168          * fix .rel.dyn relocations
 169          */
 170         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 171         sub     r9, r6, r0              /* r9 <- relocation offset */
 172         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 173         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 174         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 175         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 176         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 177         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 178 fixloop:
 179         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 180         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 181         ldr     r1, [r2, #4]
 182         and     r7, r1, #0xff
 183         cmp     r7, #23                 /* relative fixup? */
 184         beq     fixrel
 185         cmp     r7, #2                  /* absolute fixup? */
 186         beq     fixabs
 187         /* ignore unknown type of fixup */
 188         b       fixnext
 189 fixabs:
 190         /* absolute fix: set location to (offset) symbol value */
 191         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 192         add     r1, r10, r1             /* r1 <- address of symbol in table */
 193         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 194         add     r1, r1, r9              /* r1 <- relocated sym addr */
 195         b       fixnext
 196 fixrel:
 197         /* relative fix: increase location by offset */
 198         ldr     r1, [r0]
 199         add     r1, r1, r9
 200 fixnext:
 201         str     r1, [r0]
 202         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 203         cmp     r2, r3
 204         blo     fixloop
 205 #endif
 206
 207 relocate_done:
 208
 209         bx      lr
 210
 211 _rel_dyn_start_ofs:
 212         .word __rel_dyn_start - _start
 213 _rel_dyn_end_ofs:
 214         .word __rel_dyn_end - _start
 215 _dynsym_start_ofs:
 216         .word __dynsym_start - _start
 217
 218         .globl  c_runtime_cpu_setup
 219 c_runtime_cpu_setup:
 220
 221         bx      lr
 222
 223 /*
 224  *************************************************************************
 225  *
 226  * CPU_init_critical registers
 227  *
 228  * setup important registers
 229  * setup memory timing
 230  *
 231  *************************************************************************
 232  */
 233
 234 #define INTCON (0x01c00000+0x200000)
 235 #define INTMSK (0x01c00000+0x20000c)
 236 #define LOCKTIME (0x01c00000+0x18000c)
 237 #define PLLCON (0x01c00000+0x180000)
 238 #define CLKCON (0x01c00000+0x180004)
 239 #define WTCON (0x01c00000+0x130000)
 240 cpu_init_crit:
 241         /* disable watch dog */
 242         ldr     r0, =WTCON
 243         ldr     r1, =0x0
 244         str     r1, [r0]
 245
 246         /*
 247          * mask all IRQs by clearing all bits in the INTMRs
 248          */
 249         ldr     r1,=INTMSK
 250         ldr     r0, =0x03fffeff
 251         str     r0, [r1]
 252
 253         ldr     r1, =INTCON
 254         ldr     r0, =0x05
 255         str     r0, [r1]
 256
 257         /* Set Clock Control Register */
 258         ldr     r1, =LOCKTIME
 259         ldrb    r0, =800
 260         strb    r0, [r1]
 261
 262         ldr     r1, =PLLCON
 263
 264 #if CONFIG_S3C44B0_CLOCK_SPEED==66
 265         ldr     r0, =0x34031    /* 66MHz (Quartz=11MHz) */
 266 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
 267         ldr     r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz  */
 268 #else
 269 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
 270 #endif
 271
 272         str     r0, [r1]
 273
 274         ldr     r1,=CLKCON
 275         ldr     r0, =0x7ff8
 276         str     r0, [r1]
 277
 278         mov     pc, lr
 279
 280
 281 /*************************************************/
 282 /*      interrupt vectors       */
 283 /*************************************************/
 284 real_vectors:
 285         b       reset
 286         b       undefined_instruction
 287         b       software_interrupt
 288         b       prefetch_abort
 289         b       data_abort
 290         b       not_used
 291         b       irq
 292         b       fiq
 293
 294 /*************************************************/
 295
 296 undefined_instruction:
 297         mov     r6, #3
 298         b       reset
 299
 300 software_interrupt:
 301         mov     r6, #4
 302         b       reset
 303
 304 prefetch_abort:
 305         mov     r6, #5
 306         b       reset
 307
 308 data_abort:
 309         mov     r6, #6
 310         b       reset
 311
 312 not_used:
 313         /* we *should* never reach this */
 314         mov     r6, #7
 315         b       reset
 316
 317 irq:
 318         mov     r6, #8
 319         b       reset
 320
 321 fiq:
 322         mov     r6, #9
 323         b       reset