arch/arm/cpu/s3c44b0/start.S

   1 /*
   2  * Startup Code for S3C44B0 CPU-core
   3  *
   4  * (C) Copyright 2004
   5  * DAVE Srl
   6  *
   7  * http://www.dave-tech.it
   8  * http://www.wawnet.biz
   9  * mailto:info@wawnet.biz
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <asm-offsets.h>
  31 #include <config.h>
  32 #include <version.h>
  33
  34 /*
  35  * Jump vector table
  36  */
  37
  38
  39 .globl _start
  40 _start: b       reset
  41         add     pc, pc, #0x0c000000
  42         add     pc, pc, #0x0c000000
  43         add     pc, pc, #0x0c000000
  44         add     pc, pc, #0x0c000000
  45         add     pc, pc, #0x0c000000
  46         add     pc, pc, #0x0c000000
  47         add     pc, pc, #0x0c000000
  48
  49         .balignl 16,0xdeadbeef
  50
  51
  52 /*
  53  *************************************************************************
  54  *
  55  * Startup Code (reset vector)
  56  *
  57  * do important init only if we don't start from memory!
  58  * relocate u-boot to ram
  59  * setup stack
  60  * jump to second stage
  61  *
  62  *************************************************************************
  63  */
  64
  65 .globl _TEXT_BASE
  66 _TEXT_BASE:
  67         .word   CONFIG_SYS_TEXT_BASE
  68
  69 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  70 .globl _armboot_start
  71 _armboot_start:
  72         .word _start
  73 #endif
  74
  75 /*
  76  * These are defined in the board-specific linker script.
  77  */
  78 .globl _bss_start
  79 _bss_start:
  80         .word __bss_start
  81
  82 .globl _bss_end
  83 _bss_end:
  84         .word _end
  85
  86 #ifdef CONFIG_USE_IRQ
  87 /* IRQ stack memory (calculated at run-time) */
  88 .globl IRQ_STACK_START
  89 IRQ_STACK_START:
  90         .word   0x0badc0de
  91
  92 /* IRQ stack memory (calculated at run-time) */
  93 .globl FIQ_STACK_START
  94 FIQ_STACK_START:
  95         .word 0x0badc0de
  96 #endif
  97
  98 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  99 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 100 .globl IRQ_STACK_START_IN
 101 IRQ_STACK_START_IN:
 102         .word   0x0badc0de
 103
 104 .globl _datarel_start
 105 _datarel_start:
 106         .word __datarel_start
 107
 108 .globl _datarelrolocal_start
 109 _datarelrolocal_start:
 110         .word __datarelrolocal_start
 111
 112 .globl _datarellocal_start
 113 _datarellocal_start:
 114         .word __datarellocal_start
 115
 116 .globl _datarelro_start
 117 _datarelro_start:
 118         .word __datarelro_start
 119
 120 .globl _got_start
 121 _got_start:
 122         .word __got_start
 123
 124 .globl _got_end
 125 _got_end:
 126         .word __got_end
 127
 128 /*
 129  * the actual reset code
 130  */
 131
 132 reset:
 133         /*
 134          * set the cpu to SVC32 mode
 135          */
 136         mrs     r0,cpsr
 137         bic     r0,r0,#0x1f
 138         orr     r0,r0,#0xd3
 139         msr     cpsr,r0
 140
 141         /*
 142          * we do sys-critical inits only at reboot,
 143          * not when booting from ram!
 144          */
 145 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 146         bl      cpu_init_crit
 147         /*
 148          * before relocating, we have to setup RAM timing
 149          * because memory timing is board-dependend, you will
 150          * find a lowlevel_init.S in your board directory.
 151          */
 152         bl      lowlevel_init
 153 #endif
 154
 155 /* Set stackpointer in internal RAM to call board_init_f */
 156 call_board_init_f:
 157         ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 158         ldr     r0,=0x00000000
 159         bl      board_init_f
 160
 161 /*------------------------------------------------------------------------------*/
 162
 163 /*
 164  * void relocate_code (addr_sp, gd, addr_moni)
 165  *
 166  * This "function" does not return, instead it continues in RAM
 167  * after relocating the monitor code.
 168  *
 169  */
 170         .globl  relocate_code
 171 relocate_code:
 172         mov     r4, r0  /* save addr_sp */
 173         mov     r5, r1  /* save addr of gd */
 174         mov     r6, r2  /* save addr of destination */
 175         mov     r7, r2  /* save addr of destination */
 176
 177         /* Set up the stack                                                 */
 178 stack_setup:
 179         mov     sp, r4
 180
 181         adr     r0, _start
 182         ldr     r2, _TEXT_BASE
 183         ldr     r3, _bss_start
 184         sub     r2, r3, r2              /* r2 <- size of armboot            */
 185         add     r2, r0, r2              /* r2 <- source end address         */
 186         cmp     r0, r6
 187         beq     clear_bss
 188
 189 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 190 copy_loop:
 191         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 192         stmia   r6!, {r9-r10}           /* copy to   target address [r1]    */
 193         cmp     r0, r2                  /* until source end address [r2]    */
 194         blo     copy_loop
 195
 196 #ifndef CONFIG_PRELOADER
 197         /* fix got entries */
 198         ldr     r1, _TEXT_BASE          /* Text base */
 199         mov     r0, r7                  /* reloc addr */
 200         ldr     r2, _got_start          /* addr in Flash */
 201         ldr     r3, _got_end            /* addr in Flash */
 202         sub     r3, r3, r1
 203         add     r3, r3, r0
 204         sub     r2, r2, r1
 205         add     r2, r2, r0
 206
 207 fixloop:
 208         ldr     r4, [r2]
 209         sub     r4, r4, r1
 210         add     r4, r4, r0
 211         str     r4, [r2]
 212         add     r2, r2, #4
 213         cmp     r2, r3
 214         blo     fixloop
 215 #endif
 216 /*
 217         now copy to sram the interrupt vector
 218 */
 219         adr     r0, real_vectors
 220         add     r2, r0, #1024
 221         ldr     r1, =0x0c000000
 222         add     r1, r1, #0x08
 223 vector_copy_loop:
 224         ldmia   r0!, {r3-r10}
 225         stmia   r1!, {r3-r10}
 226         cmp     r0, r2
 227         blo     vector_copy_loop
 228 #endif  /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 229
 230 clear_bss:
 231 #ifndef CONFIG_PRELOADER
 232         ldr     r0, _bss_start
 233         ldr     r1, _bss_end
 234         ldr     r3, _TEXT_BASE          /* Text base */
 235         mov     r4, r7                  /* reloc addr */
 236         sub     r0, r0, r3
 237         add     r0, r0, r4
 238         sub     r1, r1, r3
 239         add     r1, r1, r4
 240         mov     r2, #0x00000000         /* clear                            */
 241
 242 clbss_l:str     r2, [r0]                /* clear loop...                    */
 243         add     r0, r0, #4
 244         cmp     r0, r1
 245         bne     clbss_l
 246
 247         bl coloured_LED_init
 248         bl red_LED_on
 249 #endif
 250
 251 /*
 252  * We are done. Do not return, instead branch to second part of board
 253  * initialization, now running from RAM.
 254  */
 255         ldr     r0, _TEXT_BASE
 256         ldr     r2, _board_init_r
 257         sub     r2, r2, r0
 258         add     r2, r2, r7      /* position from board_init_r in RAM */
 259         /* setup parameters for board_init_r */
 260         mov     r0, r5          /* gd_t */
 261         mov     r1, r7          /* dest_addr */
 262         /* jump to it ... */
 263         mov     lr, r2
 264         mov     pc, lr
 265
 266 _board_init_r: .word board_init_r
 267
 268 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
 269 /*
 270  * the actual reset code
 271  */
 272
 273 reset:
 274         /*
 275          * set the cpu to SVC32 mode
 276          */
 277         mrs     r0,cpsr
 278         bic     r0,r0,#0x1f
 279         orr     r0,r0,#0x13
 280         msr     cpsr,r0
 281
 282         /*
 283          * we do sys-critical inits only at reboot,
 284          * not when booting from ram!
 285          */
 286
 287 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 288         bl      cpu_init_crit
 289         /*
 290          * before relocating, we have to setup RAM timing
 291          * because memory timing is board-dependend, you will
 292          * find a lowlevel_init.S in your board directory.
 293          */
 294         bl      lowlevel_init
 295 #endif
 296
 297 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 298 relocate:                               /* relocate U-Boot to RAM           */
 299         adr     r0, _start              /* r0 <- current position of code   */
 300         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 301         cmp     r0, r1                  /* don't reloc during debug         */
 302         beq     stack_setup
 303
 304         ldr     r2, _armboot_start
 305         ldr     r3, _bss_start
 306         sub     r2, r3, r2              /* r2 <- size of armboot            */
 307         add     r2, r0, r2              /* r2 <- source end address         */
 308
 309 copy_loop:
 310         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 311         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 312         cmp     r0, r2                  /* until source end address [r2]    */
 313         blo     copy_loop
 314
 315 /*
 316         now copy to sram the interrupt vector
 317 */
 318         adr     r0, real_vectors
 319         add     r2, r0, #1024
 320         ldr     r1, =0x0c000000
 321         add     r1, r1, #0x08
 322 vector_copy_loop:
 323         ldmia   r0!, {r3-r10}
 324         stmia   r1!, {r3-r10}
 325         cmp     r0, r2
 326         blo     vector_copy_loop
 327 #endif  /* CONFIG_SKIP_RELOCATE_UBOOT */
 328
 329         /* Set up the stack                                                 */
 330 stack_setup:
 331         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 332         sub     r0, r0, #CONFIG_SYS_MALLOC_LEN  /* malloc area                      */
 333         sub     r0, r0, #GENERATED_GBL_DATA_SIZE /* bdinfo                        */
 334 #ifdef CONFIG_USE_IRQ
 335         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 336 #endif
 337         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 338         bic     sp, sp, #7              /* 8-byte alignment for ABI compliance */
 339
 340         ldr     pc, _start_armboot
 341
 342 _start_armboot: .word start_armboot
 343
 344 #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
 345
 346 /*
 347  *************************************************************************
 348  *
 349  * CPU_init_critical registers
 350  *
 351  * setup important registers
 352  * setup memory timing
 353  *
 354  *************************************************************************
 355  */
 356
 357 #define INTCON (0x01c00000+0x200000)
 358 #define INTMSK (0x01c00000+0x20000c)
 359 #define LOCKTIME (0x01c00000+0x18000c)
 360 #define PLLCON (0x01c00000+0x180000)
 361 #define CLKCON (0x01c00000+0x180004)
 362 #define WTCON (0x01c00000+0x130000)
 363 cpu_init_crit:
 364         /* disable watch dog */
 365         ldr     r0, =WTCON
 366         ldr     r1, =0x0
 367         str     r1, [r0]
 368
 369         /*
 370          * mask all IRQs by clearing all bits in the INTMRs
 371          */
 372         ldr     r1,=INTMSK
 373         ldr     r0, =0x03fffeff
 374         str     r0, [r1]
 375
 376         ldr     r1, =INTCON
 377         ldr     r0, =0x05
 378         str     r0, [r1]
 379
 380         /* Set Clock Control Register */
 381         ldr     r1, =LOCKTIME
 382         ldrb    r0, =800
 383         strb    r0, [r1]
 384
 385         ldr     r1, =PLLCON
 386
 387 #if CONFIG_S3C44B0_CLOCK_SPEED==66
 388         ldr     r0, =0x34031    /* 66MHz (Quartz=11MHz) */
 389 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
 390         ldr     r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz  */
 391 #else
 392 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
 393 #endif
 394
 395         str     r0, [r1]
 396
 397         ldr     r1,=CLKCON
 398         ldr     r0, =0x7ff8
 399         str     r0, [r1]
 400
 401         mov     pc, lr
 402
 403
 404 /*************************************************/
 405 /*      interrupt vectors       */
 406 /*************************************************/
 407 real_vectors:
 408         b       reset
 409         b       undefined_instruction
 410         b       software_interrupt
 411         b       prefetch_abort
 412         b       data_abort
 413         b       not_used
 414         b       irq
 415         b       fiq
 416
 417 /*************************************************/
 418
 419 undefined_instruction:
 420         mov     r6, #3
 421         b       reset
 422
 423 software_interrupt:
 424         mov     r6, #4
 425         b       reset
 426
 427 prefetch_abort:
 428         mov     r6, #5
 429         b       reset
 430
 431 data_abort:
 432         mov     r6, #6
 433         b       reset
 434
 435 not_used:
 436         /* we *should* never reach this */
 437         mov     r6, #7
 438         b       reset
 439
 440 irq:
 441         mov     r6, #8
 442         b       reset
 443
 444 fiq:
 445         mov     r6, #9
 446         b       reset