arch/arm/cpu/sa1100/start.S

   1 /*
   2  *  armboot - Startup Code for SA1100 CPU
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (c) 2001  Alex Züpke <azu@sysgo.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <asm-offsets.h>
  29 #include <config.h>
  30 #include <version.h>
  31
  32 /*
  33  *************************************************************************
  34  *
  35  * Jump vector table as in table 3.1 in [1]
  36  *
  37  *************************************************************************
  38  */
  39
  40
  41 .globl _start
  42 _start: b       reset
  43         ldr     pc, _undefined_instruction
  44         ldr     pc, _software_interrupt
  45         ldr     pc, _prefetch_abort
  46         ldr     pc, _data_abort
  47         ldr     pc, _not_used
  48         ldr     pc, _irq
  49         ldr     pc, _fiq
  50
  51 _undefined_instruction: .word undefined_instruction
  52 _software_interrupt:    .word software_interrupt
  53 _prefetch_abort:        .word prefetch_abort
  54 _data_abort:            .word data_abort
  55 _not_used:              .word not_used
  56 _irq:                   .word irq
  57 _fiq:                   .word fiq
  58
  59         .balignl 16,0xdeadbeef
  60
  61
  62 /*
  63  *************************************************************************
  64  *
  65  * Startup Code (reset vector)
  66  *
  67  * do important init only if we don't start from memory!
  68  * relocate armboot to ram
  69  * setup stack
  70  * jump to second stage
  71  *
  72  *************************************************************************
  73  */
  74
  75 .globl _TEXT_BASE
  76 _TEXT_BASE:
  77 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  78         .word   CONFIG_SPL_TEXT_BASE
  79 #else
  80         .word   CONFIG_SYS_TEXT_BASE
  81 #endif
  82
  83 /*
  84  * These are defined in the board-specific linker script.
  85  * Subtracting _start from them lets the linker put their
  86  * relative position in the executable instead of leaving
  87  * them null.
  88  */
  89 .globl _bss_start_ofs
  90 _bss_start_ofs:
  91         .word __bss_start - _start
  92
  93 .globl _image_copy_end_ofs
  94 _image_copy_end_ofs:
  95         .word __image_copy_end - _start
  96
  97 .globl _bss_end_ofs
  98 _bss_end_ofs:
  99         .word __bss_end - _start
 100
 101 .globl _end_ofs
 102 _end_ofs:
 103         .word _end - _start
 104
 105 #ifdef CONFIG_USE_IRQ
 106 /* IRQ stack memory (calculated at run-time) */
 107 .globl IRQ_STACK_START
 108 IRQ_STACK_START:
 109         .word   0x0badc0de
 110
 111 /* IRQ stack memory (calculated at run-time) */
 112 .globl FIQ_STACK_START
 113 FIQ_STACK_START:
 114         .word 0x0badc0de
 115 #endif
 116
 117 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 118 .globl IRQ_STACK_START_IN
 119 IRQ_STACK_START_IN:
 120         .word   0x0badc0de
 121
 122 /*
 123  * the actual reset code
 124  */
 125
 126 reset:
 127         /*
 128          * set the cpu to SVC32 mode
 129          */
 130         mrs     r0,cpsr
 131         bic     r0,r0,#0x1f
 132         orr     r0,r0,#0xd3
 133         msr     cpsr,r0
 134
 135         /*
 136          * we do sys-critical inits only at reboot,
 137          * not when booting from ram!
 138          */
 139 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 140         bl      cpu_init_crit
 141 #endif
 142
 143         bl      _main
 144
 145 /*------------------------------------------------------------------------------*/
 146
 147 /*
 148  * void relocate_code (addr_sp, gd, addr_moni)
 149  *
 150  * This function relocates the monitor code.
 151  */
 152         .globl  relocate_code
 153 relocate_code:
 154         mov     r4, r0  /* save addr_sp */
 155         mov     r5, r1  /* save addr of gd */
 156         mov     r6, r2  /* save addr of destination */
 157
 158         adr     r0, _start
 159         subs    r9, r6, r0              /* r9 <- relocation offset */
 160         beq     relocate_done           /* skip relocation */
 161         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 162         ldr     r3, _image_copy_end_ofs
 163         add     r2, r0, r3              /* r2 <- source end address         */
 164
 165 copy_loop:
 166         ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
 167         stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
 168         cmp     r0, r2                  /* until source end address [r2]    */
 169         blo     copy_loop
 170
 171 #ifndef CONFIG_SPL_BUILD
 172         /*
 173          * fix .rel.dyn relocations
 174          */
 175         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 176         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 177         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 178         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 179         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 180         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 181         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 182 fixloop:
 183         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 184         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 185         ldr     r1, [r2, #4]
 186         and     r7, r1, #0xff
 187         cmp     r7, #23                 /* relative fixup? */
 188         beq     fixrel
 189         cmp     r7, #2                  /* absolute fixup? */
 190         beq     fixabs
 191         /* ignore unknown type of fixup */
 192         b       fixnext
 193 fixabs:
 194         /* absolute fix: set location to (offset) symbol value */
 195         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 196         add     r1, r10, r1             /* r1 <- address of symbol in table */
 197         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 198         add     r1, r1, r9              /* r1 <- relocated sym addr */
 199         b       fixnext
 200 fixrel:
 201         /* relative fix: increase location by offset */
 202         ldr     r1, [r0]
 203         add     r1, r1, r9
 204 fixnext:
 205         str     r1, [r0]
 206         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 207         cmp     r2, r3
 208         blo     fixloop
 209 #endif
 210
 211 relocate_done:
 212
 213         mov     pc, lr
 214
 215 _rel_dyn_start_ofs:
 216         .word __rel_dyn_start - _start
 217 _rel_dyn_end_ofs:
 218         .word __rel_dyn_end - _start
 219 _dynsym_start_ofs:
 220         .word __dynsym_start - _start
 221
 222         .globl  c_runtime_cpu_setup
 223 c_runtime_cpu_setup:
 224
 225         mov     pc, lr
 226
 227 /*
 228  *************************************************************************
 229  *
 230  * CPU_init_critical registers
 231  *
 232  * setup important registers
 233  * setup memory timing
 234  *
 235  *************************************************************************
 236  */
 237
 238
 239 /* Interrupt-Controller base address */
 240 IC_BASE:        .word   0x90050000
 241 #define ICMR    0x04
 242
 243
 244 /* Reset-Controller */
 245 RST_BASE:               .word   0x90030000
 246 #define RSRR    0x00
 247 #define RCSR    0x04
 248
 249
 250 /* PWR */
 251 PWR_BASE:               .word   0x90020000
 252 #define PSPR    0x08
 253 #define PPCR    0x14
 254 cpuspeed:               .word   CONFIG_SYS_CPUSPEED
 255
 256
 257 cpu_init_crit:
 258         /*
 259          * mask all IRQs
 260          */
 261         ldr     r0, IC_BASE
 262         mov     r1, #0x00
 263         str     r1, [r0, #ICMR]
 264
 265         /* set clock speed */
 266         ldr     r0, PWR_BASE
 267         ldr     r1, cpuspeed
 268         str     r1, [r0, #PPCR]
 269
 270         /*
 271          * before relocating, we have to setup RAM timing
 272          * because memory timing is board-dependend, you will
 273          * find a lowlevel_init.S in your board directory.
 274          */
 275         mov     ip,     lr
 276         bl      lowlevel_init
 277         mov     lr,     ip
 278
 279         /*
 280          * disable MMU stuff and enable I-cache
 281          */
 282         mrc     p15,0,r0,c1,c0
 283         bic     r0, r0, #0x00002000     @ clear bit 13 (X)
 284         bic     r0, r0, #0x0000000f     @ clear bits 3-0 (WCAM)
 285         orr     r0, r0, #0x00001000     @ set bit 12 (I) Icache
 286         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 287         mcr     p15,0,r0,c1,c0
 288
 289         /*
 290          * flush v4 I/D caches
 291          */
 292         mov     r0, #0
 293         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 294         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 295
 296         mov     pc, lr
 297
 298
 299 /*
 300  *************************************************************************
 301  *
 302  * Interrupt handling
 303  *
 304  *************************************************************************
 305  */
 306
 307 @
 308 @ IRQ stack frame.
 309 @
 310 #define S_FRAME_SIZE    72
 311
 312 #define S_OLD_R0        68
 313 #define S_PSR           64
 314 #define S_PC            60
 315 #define S_LR            56
 316 #define S_SP            52
 317
 318 #define S_IP            48
 319 #define S_FP            44
 320 #define S_R10           40
 321 #define S_R9            36
 322 #define S_R8            32
 323 #define S_R7            28
 324 #define S_R6            24
 325 #define S_R5            20
 326 #define S_R4            16
 327 #define S_R3            12
 328 #define S_R2            8
 329 #define S_R1            4
 330 #define S_R0            0
 331
 332 #define MODE_SVC 0x13
 333 #define I_BIT    0x80
 334
 335 /*
 336  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 337  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 338  */
 339
 340         .macro  bad_save_user_regs
 341         sub     sp, sp, #S_FRAME_SIZE
 342         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 343         add     r8, sp, #S_PC
 344
 345         ldr     r2, IRQ_STACK_START_IN
 346         ldmia   r2, {r2 - r4}                   @ get pc, cpsr, old_r0
 347         add     r0, sp, #S_FRAME_SIZE           @ restore sp_SVC
 348
 349         add     r5, sp, #S_SP
 350         mov     r1, lr
 351         stmia   r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
 352         mov     r0, sp
 353         .endm
 354
 355         .macro  irq_save_user_regs
 356         sub     sp, sp, #S_FRAME_SIZE
 357         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 358         add     r8, sp, #S_PC
 359         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 360         str     lr, [r8, #0]                    @ Save calling PC
 361         mrs     r6, spsr
 362         str     r6, [r8, #4]                    @ Save CPSR
 363         str     r0, [r8, #8]                    @ Save OLD_R0
 364         mov     r0, sp
 365         .endm
 366
 367         .macro  irq_restore_user_regs
 368         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 369         mov     r0, r0
 370         ldr     lr, [sp, #S_PC]                 @ Get PC
 371         add     sp, sp, #S_FRAME_SIZE
 372         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 373         .endm
 374
 375         .macro get_bad_stack
 376         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 377
 378         str     lr, [r13]                       @ save caller lr / spsr
 379         mrs     lr, spsr
 380         str     lr, [r13, #4]
 381
 382         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 383         msr     spsr_c, r13
 384         mov     lr, pc
 385         movs    pc, lr
 386         .endm
 387
 388         .macro get_irq_stack                    @ setup IRQ stack
 389         ldr     sp, IRQ_STACK_START
 390         .endm
 391
 392         .macro get_fiq_stack                    @ setup FIQ stack
 393         ldr     sp, FIQ_STACK_START
 394         .endm
 395
 396 /*
 397  * exception handlers
 398  */
 399         .align  5
 400 undefined_instruction:
 401         get_bad_stack
 402         bad_save_user_regs
 403         bl      do_undefined_instruction
 404
 405         .align  5
 406 software_interrupt:
 407         get_bad_stack
 408         bad_save_user_regs
 409         bl      do_software_interrupt
 410
 411         .align  5
 412 prefetch_abort:
 413         get_bad_stack
 414         bad_save_user_regs
 415         bl      do_prefetch_abort
 416
 417         .align  5
 418 data_abort:
 419         get_bad_stack
 420         bad_save_user_regs
 421         bl      do_data_abort
 422
 423         .align  5
 424 not_used:
 425         get_bad_stack
 426         bad_save_user_regs
 427         bl      do_not_used
 428
 429 #ifdef CONFIG_USE_IRQ
 430
 431         .align  5
 432 irq:
 433         get_irq_stack
 434         irq_save_user_regs
 435         bl      do_irq
 436         irq_restore_user_regs
 437
 438         .align  5
 439 fiq:
 440         get_fiq_stack
 441         /* someone ought to write a more effiction fiq_save_user_regs */
 442         irq_save_user_regs
 443         bl      do_fiq
 444         irq_restore_user_regs
 445
 446 #else
 447
 448         .align  5
 449 irq:
 450         get_bad_stack
 451         bad_save_user_regs
 452         bl      do_irq
 453
 454         .align  5
 455 fiq:
 456         get_bad_stack
 457         bad_save_user_regs
 458         bl      do_fiq
 459
 460 #endif
 461
 462         .align  5
 463 .globl reset_cpu
 464 reset_cpu:
 465         ldr     r0, RST_BASE
 466         mov     r1, #0x0                        @ set bit 3-0 ...
 467         str     r1, [r0, #RCSR]                 @ ... to clear in RCSR
 468         mov     r1, #0x1
 469         str     r1, [r0, #RSRR]                 @ and perform reset
 470         b       reset_cpu                       @ silly, but repeat endlessly