arch/arm/cpu/sa1100/start.S

   1 /*
   2  *  armboot - Startup Code for SA1100 CPU
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (c) 2001  Alex Züpke <azu@sysgo.de>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <asm-offsets.h>
  13 #include <config.h>
  14
  15 /*
  16  *************************************************************************
  17  *
  18  * Startup Code (reset vector)
  19  *
  20  * do important init only if we don't start from memory!
  21  * relocate armboot to ram
  22  * setup stack
  23  * jump to second stage
  24  *
  25  *************************************************************************
  26  */
  27
  28         .globl  reset
  29
  30 reset:
  31         /*
  32          * set the cpu to SVC32 mode
  33          */
  34         mrs     r0,cpsr
  35         bic     r0,r0,#0x1f
  36         orr     r0,r0,#0xd3
  37         msr     cpsr,r0
  38
  39         /*
  40          * we do sys-critical inits only at reboot,
  41          * not when booting from ram!
  42          */
  43 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  44         bl      cpu_init_crit
  45 #endif
  46
  47         bl      _main
  48
  49 /*------------------------------------------------------------------------------*/
  50
  51         .globl  c_runtime_cpu_setup
  52 c_runtime_cpu_setup:
  53
  54         mov     pc, lr
  55
  56 /*
  57  *************************************************************************
  58  *
  59  * CPU_init_critical registers
  60  *
  61  * setup important registers
  62  * setup memory timing
  63  *
  64  *************************************************************************
  65  */
  66
  67
  68 /* Interrupt-Controller base address */
  69 IC_BASE:        .word   0x90050000
  70 #define ICMR    0x04
  71
  72
  73 /* Reset-Controller */
  74 RST_BASE:               .word   0x90030000
  75 #define RSRR    0x00
  76 #define RCSR    0x04
  77
  78
  79 /* PWR */
  80 PWR_BASE:               .word   0x90020000
  81 #define PSPR    0x08
  82 #define PPCR    0x14
  83 cpuspeed:               .word   CONFIG_SYS_CPUSPEED
  84
  85
  86 cpu_init_crit:
  87         /*
  88          * mask all IRQs
  89          */
  90         ldr     r0, IC_BASE
  91         mov     r1, #0x00
  92         str     r1, [r0, #ICMR]
  93
  94         /* set clock speed */
  95         ldr     r0, PWR_BASE
  96         ldr     r1, cpuspeed
  97         str     r1, [r0, #PPCR]
  98
  99 #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 100         /*
 101          * before relocating, we have to setup RAM timing
 102          * because memory timing is board-dependend, you will
 103          * find a lowlevel_init.S in your board directory.
 104          */
 105         mov     ip,     lr
 106         bl      lowlevel_init
 107         mov     lr,     ip
 108 #endif
 109
 110         /*
 111          * disable MMU stuff and enable I-cache
 112          */
 113         mrc     p15,0,r0,c1,c0
 114         bic     r0, r0, #0x00002000     @ clear bit 13 (X)
 115         bic     r0, r0, #0x0000000f     @ clear bits 3-0 (WCAM)
 116         orr     r0, r0, #0x00001000     @ set bit 12 (I) Icache
 117         orr     r0, r0, #0x00000002     @ set bit 1 (A) Align
 118         mcr     p15,0,r0,c1,c0
 119
 120         /*
 121          * flush v4 I/D caches
 122          */
 123         mov     r0, #0
 124         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 125         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 126
 127         mov     pc, lr