arch/arm/cpu/sa1100/start.S

   1 /*
   2  *  armboot - Startup Code for SA1100 CPU
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (c) 2001  Alex Züpke <azu@sysgo.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <asm-offsets.h>
  29 #include <config.h>
  30 #include <version.h>
  31
  32 /*
  33  *************************************************************************
  34  *
  35  * Jump vector table as in table 3.1 in [1]
  36  *
  37  *************************************************************************
  38  */
  39
  40
  41 .globl _start
  42 _start: b       reset
  43         ldr     pc, _undefined_instruction
  44         ldr     pc, _software_interrupt
  45         ldr     pc, _prefetch_abort
  46         ldr     pc, _data_abort
  47         ldr     pc, _not_used
  48         ldr     pc, _irq
  49         ldr     pc, _fiq
  50
  51 _undefined_instruction: .word undefined_instruction
  52 _software_interrupt:    .word software_interrupt
  53 _prefetch_abort:        .word prefetch_abort
  54 _data_abort:            .word data_abort
  55 _not_used:              .word not_used
  56 _irq:                   .word irq
  57 _fiq:                   .word fiq
  58
  59         .balignl 16,0xdeadbeef
  60
  61
  62 /*
  63  *************************************************************************
  64  *
  65  * Startup Code (reset vector)
  66  *
  67  * do important init only if we don't start from memory!
  68  * relocate armboot to ram
  69  * setup stack
  70  * jump to second stage
  71  *
  72  *************************************************************************
  73  */
  74
  75 .globl _TEXT_BASE
  76 _TEXT_BASE:
  77         .word   CONFIG_SYS_TEXT_BASE
  78
  79 /*
  80  * These are defined in the board-specific linker script.
  81  * Subtracting _start from them lets the linker put their
  82  * relative position in the executable instead of leaving
  83  * them null.
  84  */
  85 .globl _bss_start_ofs
  86 _bss_start_ofs:
  87         .word __bss_start - _start
  88
  89 .globl _bss_end_ofs
  90 _bss_end_ofs:
  91         .word _end - _start
  92
  93 #ifdef CONFIG_USE_IRQ
  94 /* IRQ stack memory (calculated at run-time) */
  95 .globl IRQ_STACK_START
  96 IRQ_STACK_START:
  97         .word   0x0badc0de
  98
  99 /* IRQ stack memory (calculated at run-time) */
 100 .globl FIQ_STACK_START
 101 FIQ_STACK_START:
 102         .word 0x0badc0de
 103 #endif
 104
 105 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 106 .globl IRQ_STACK_START_IN
 107 IRQ_STACK_START_IN:
 108         .word   0x0badc0de
 109
 110 /*
 111  * the actual reset code
 112  */
 113
 114 reset:
 115         /*
 116          * set the cpu to SVC32 mode
 117          */
 118         mrs     r0,cpsr
 119         bic     r0,r0,#0x1f
 120         orr     r0,r0,#0xd3
 121         msr     cpsr,r0
 122
 123         /*
 124          * we do sys-critical inits only at reboot,
 125          * not when booting from ram!
 126          */
 127 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 128         bl      cpu_init_crit
 129 #endif
 130
 131 /* Set stackpointer in internal RAM to call board_init_f */
 132 call_board_init_f:
 133         ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 134         bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
 135         ldr     r0,=0x00000000
 136         bl      board_init_f
 137
 138 /*------------------------------------------------------------------------------*/
 139
 140 /*
 141  * void relocate_code (addr_sp, gd, addr_moni)
 142  *
 143  * This "function" does not return, instead it continues in RAM
 144  * after relocating the monitor code.
 145  *
 146  */
 147         .globl  relocate_code
 148 relocate_code:
 149         mov     r4, r0  /* save addr_sp */
 150         mov     r5, r1  /* save addr of gd */
 151         mov     r6, r2  /* save addr of destination */
 152
 153         /* Set up the stack                                                 */
 154 stack_setup:
 155         mov     sp, r4
 156
 157         adr     r0, _start
 158         cmp     r0, r6
 159         beq     clear_bss               /* skip relocation */
 160         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 161         ldr     r3, _bss_start_ofs
 162         add     r2, r0, r3              /* r2 <- source end address         */
 163
 164 copy_loop:
 165         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 166         stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 167         cmp     r0, r2                  /* until source end address [r2]    */
 168         blo     copy_loop
 169
 170 #ifndef CONFIG_PRELOADER
 171         /*
 172          * fix .rel.dyn relocations
 173          */
 174         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 175         sub     r9, r6, r0              /* r9 <- relocation offset */
 176         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 177         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 178         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 179         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 180         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 181         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 182 fixloop:
 183         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 184         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 185         ldr     r1, [r2, #4]
 186         and     r7, r1, #0xff
 187         cmp     r7, #23                 /* relative fixup? */
 188         beq     fixrel
 189         cmp     r7, #2                  /* absolute fixup? */
 190         beq     fixabs
 191         /* ignore unknown type of fixup */
 192         b       fixnext
 193 fixabs:
 194         /* absolute fix: set location to (offset) symbol value */
 195         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 196         add     r1, r10, r1             /* r1 <- address of symbol in table */
 197         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 198         add     r1, r1, r9              /* r1 <- relocated sym addr */
 199         b       fixnext
 200 fixrel:
 201         /* relative fix: increase location by offset */
 202         ldr     r1, [r0]
 203         add     r1, r1, r9
 204 fixnext:
 205         str     r1, [r0]
 206         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 207         cmp     r2, r3
 208         blo     fixloop
 209 #endif
 210
 211 clear_bss:
 212 #ifndef CONFIG_PRELOADER
 213         ldr     r0, _bss_start_ofs
 214         ldr     r1, _bss_end_ofs
 215         mov     r4, r6                  /* reloc addr */
 216         add     r0, r0, r4
 217         add     r1, r1, r4
 218         mov     r2, #0x00000000         /* clear                            */
 219
 220 clbss_l:str     r2, [r0]                /* clear loop...                    */
 221         add     r0, r0, #4
 222         cmp     r0, r1
 223         bne     clbss_l
 224 #endif
 225
 226 /*
 227  * We are done. Do not return, instead branch to second part of board
 228  * initialization, now running from RAM.
 229  */
 230         ldr     r0, _board_init_r_ofs
 231         adr     r1, _start
 232         add     lr, r0, r1
 233         add     lr, lr, r9
 234         /* setup parameters for board_init_r */
 235         mov     r0, r5          /* gd_t */
 236         mov     r1, r6          /* dest_addr */
 237         /* jump to it ... */
 238         mov     pc, lr
 239
 240 _board_init_r_ofs:
 241         .word board_init_r - _start
 242
 243 _rel_dyn_start_ofs:
 244         .word __rel_dyn_start - _start
 245 _rel_dyn_end_ofs:
 246         .word __rel_dyn_end - _start
 247 _dynsym_start_ofs:
 248         .word __dynsym_start - _start
 249
 250 /*
 251  *************************************************************************
 252  *
 253  * CPU_init_critical registers
 254  *
 255  * setup important registers
 256  * setup memory timing
 257  *
 258  *************************************************************************
 259  */
 260
 261
 262 /* Interupt-Controller base address */
 263 IC_BASE:        .word   0x90050000
 264 #define ICMR    0x04
 265
 266
 267 /* Reset-Controller */
 268 RST_BASE:               .word   0x90030000
 269 #define RSRR    0x00
 270 #define RCSR    0x04
 271
 272
 273 /* PWR */
 274 PWR_BASE:               .word   0x90020000
 275 #define PSPR    0x08
 276 #define PPCR    0x14
 277 cpuspeed:               .word   CONFIG_SYS_CPUSPEED
 278
 279
 280 cpu_init_crit:
 281         /*
 282          * mask all IRQs
 283          */
 284         ldr     r0, IC_BASE
 285         mov     r1, #0x00
 286         str     r1, [r0, #ICMR]
 287
 288         /* set clock speed */
 289         ldr     r0, PWR_BASE
 290         ldr     r1, cpuspeed
 291         str     r1, [r0, #PPCR]
 292
 293         /*
 294          * before relocating, we have to setup RAM timing
 295          * because memory timing is board-dependend, you will
 296          * find a lowlevel_init.S in your board directory.
 297          */
 298         mov     ip,     lr
 299         bl      lowlevel_init
 300         mov     lr,     ip
 301
 302         /*
 303          * disable MMU stuff and enable I-cache
 304          */
 305         mrc     p15,0,r0,c1,c0
 306         bic     r0, r0, #0x00002000     @ clear bit 13 (X)
 307         bic     r0, r0, #0x0000000f     @ clear bits 3-0 (WCAM)
 308         orr     r0, r0, #0x00001000     @ set bit 12 (I) Icache
 309         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 310         mcr     p15,0,r0,c1,c0
 311
 312         /*
 313          * flush v4 I/D caches
 314          */
 315         mov     r0, #0
 316         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 317         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 318
 319         mov     pc, lr
 320
 321
 322 /*
 323  *************************************************************************
 324  *
 325  * Interrupt handling
 326  *
 327  *************************************************************************
 328  */
 329
 330 @
 331 @ IRQ stack frame.
 332 @
 333 #define S_FRAME_SIZE    72
 334
 335 #define S_OLD_R0        68
 336 #define S_PSR           64
 337 #define S_PC            60
 338 #define S_LR            56
 339 #define S_SP            52
 340
 341 #define S_IP            48
 342 #define S_FP            44
 343 #define S_R10           40
 344 #define S_R9            36
 345 #define S_R8            32
 346 #define S_R7            28
 347 #define S_R6            24
 348 #define S_R5            20
 349 #define S_R4            16
 350 #define S_R3            12
 351 #define S_R2            8
 352 #define S_R1            4
 353 #define S_R0            0
 354
 355 #define MODE_SVC 0x13
 356 #define I_BIT    0x80
 357
 358 /*
 359  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 360  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 361  */
 362
 363         .macro  bad_save_user_regs
 364         sub     sp, sp, #S_FRAME_SIZE
 365         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 366         add     r8, sp, #S_PC
 367
 368         ldr     r2, IRQ_STACK_START_IN
 369         ldmia   r2, {r2 - r4}                   @ get pc, cpsr, old_r0
 370         add     r0, sp, #S_FRAME_SIZE           @ restore sp_SVC
 371
 372         add     r5, sp, #S_SP
 373         mov     r1, lr
 374         stmia   r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
 375         mov     r0, sp
 376         .endm
 377
 378         .macro  irq_save_user_regs
 379         sub     sp, sp, #S_FRAME_SIZE
 380         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 381         add     r8, sp, #S_PC
 382         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 383         str     lr, [r8, #0]                    @ Save calling PC
 384         mrs     r6, spsr
 385         str     r6, [r8, #4]                    @ Save CPSR
 386         str     r0, [r8, #8]                    @ Save OLD_R0
 387         mov     r0, sp
 388         .endm
 389
 390         .macro  irq_restore_user_regs
 391         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 392         mov     r0, r0
 393         ldr     lr, [sp, #S_PC]                 @ Get PC
 394         add     sp, sp, #S_FRAME_SIZE
 395         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 396         .endm
 397
 398         .macro get_bad_stack
 399         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 400
 401         str     lr, [r13]                       @ save caller lr / spsr
 402         mrs     lr, spsr
 403         str     lr, [r13, #4]
 404
 405         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 406         msr     spsr_c, r13
 407         mov     lr, pc
 408         movs    pc, lr
 409         .endm
 410
 411         .macro get_irq_stack                    @ setup IRQ stack
 412         ldr     sp, IRQ_STACK_START
 413         .endm
 414
 415         .macro get_fiq_stack                    @ setup FIQ stack
 416         ldr     sp, FIQ_STACK_START
 417         .endm
 418
 419 /*
 420  * exception handlers
 421  */
 422         .align  5
 423 undefined_instruction:
 424         get_bad_stack
 425         bad_save_user_regs
 426         bl      do_undefined_instruction
 427
 428         .align  5
 429 software_interrupt:
 430         get_bad_stack
 431         bad_save_user_regs
 432         bl      do_software_interrupt
 433
 434         .align  5
 435 prefetch_abort:
 436         get_bad_stack
 437         bad_save_user_regs
 438         bl      do_prefetch_abort
 439
 440         .align  5
 441 data_abort:
 442         get_bad_stack
 443         bad_save_user_regs
 444         bl      do_data_abort
 445
 446         .align  5
 447 not_used:
 448         get_bad_stack
 449         bad_save_user_regs
 450         bl      do_not_used
 451
 452 #ifdef CONFIG_USE_IRQ
 453
 454         .align  5
 455 irq:
 456         get_irq_stack
 457         irq_save_user_regs
 458         bl      do_irq
 459         irq_restore_user_regs
 460
 461         .align  5
 462 fiq:
 463         get_fiq_stack
 464         /* someone ought to write a more effiction fiq_save_user_regs */
 465         irq_save_user_regs
 466         bl      do_fiq
 467         irq_restore_user_regs
 468
 469 #else
 470
 471         .align  5
 472 irq:
 473         get_bad_stack
 474         bad_save_user_regs
 475         bl      do_irq
 476
 477         .align  5
 478 fiq:
 479         get_bad_stack
 480         bad_save_user_regs
 481         bl      do_fiq
 482
 483 #endif
 484
 485         .align  5
 486 .globl reset_cpu
 487 reset_cpu:
 488         ldr     r0, RST_BASE
 489         mov     r1, #0x0                        @ set bit 3-0 ...
 490         str     r1, [r0, #RCSR]                 @ ... to clear in RCSR
 491         mov     r1, #0x1
 492         str     r1, [r0, #RSRR]                 @ and perform reset
 493         b       reset_cpu                       @ silly, but repeat endlessly