2 * Copyright (c) 2011 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
7 /* Tegra20 pin multiplexing functions */
11 #include <asm/arch/tegra.h>
12 #include <asm/arch/pinmux.h>
16 * This defines the order of the pin mux control bits in the registers. For
17 * some reason there is no correspendence between the tristate, pin mux and
18 * pullup/pulldown registers.
21 /* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
40 /* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
59 /* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
78 /* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
97 /* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
116 /* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
135 /* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
158 * And this defines the order of the pullup/pulldown controls which are again
159 * in a different order
162 /* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
181 /* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
199 /* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
218 /* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
237 /* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
259 struct tegra_pingroup_desc
{
261 enum pmux_func funcs
[4];
262 enum pmux_func func_safe
;
263 enum pmux_vddio vddio
;
264 enum pmux_ctlid ctl_id
;
265 enum pmux_pullid pull_id
;
269 /* Converts a pmux_pingrp number to a tristate register: 0=A, 1=B, 2=C, 3=D */
270 #define TRISTATE_REG(pmux_pingrp) ((pmux_pingrp) >> 5)
272 /* Mask value for a tristate (within TRISTATE_REG(id)) */
273 #define TRISTATE_MASK(pmux_pingrp) (1 << ((pmux_pingrp) & 0x1f))
275 /* Converts a PUCTL id to a pull register: 0=A, 1=B...4=E */
276 #define PULL_REG(pmux_pullid) ((pmux_pullid) >> 4)
278 /* Converts a PUCTL id to a shift position */
279 #define PULL_SHIFT(pmux_pullid) ((pmux_pullid << 1) & 0x1f)
281 /* Converts a MUXCTL id to a ctl register: 0=A, 1=B...6=G */
282 #define MUXCTL_REG(pmux_ctlid) ((pmux_ctlid) >> 4)
284 /* Converts a MUXCTL id to a shift position */
285 #define MUXCTL_SHIFT(pmux_ctlid) ((pmux_ctlid << 1) & 0x1f)
287 /* Convenient macro for defining pin group properties */
288 #define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
290 .vddio = PMUX_VDDIO_ ## vdd, \
297 .func_safe = PMUX_FUNC_ ## f_safe, \
302 /* A normal pin group where the mux name and pull-up name match */
303 #define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe) \
304 PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
305 MUXCTL_ ## pg_name, PUCTL_ ## pg_name)
307 /* A pin group where the pull-up name doesn't have a 1-1 mapping */
308 #define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd) \
309 PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
310 MUXCTL_ ## pg_name, PUCTL_ ## pupd)
312 /* A pin group number which is not used */
313 #define PIN_RESERVED \
314 PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
316 const struct tegra_pingroup_desc tegra_soc_pingroups
[PINGRP_COUNT
] = {
317 PIN(ATA
, NAND
, IDE
, NAND
, GMI
, RSVD
, IDE
),
318 PIN(ATB
, NAND
, IDE
, NAND
, GMI
, SDIO4
, IDE
),
319 PIN(ATC
, NAND
, IDE
, NAND
, GMI
, SDIO4
, IDE
),
320 PIN(ATD
, NAND
, IDE
, NAND
, GMI
, SDIO4
, IDE
),
321 PIN(CDEV1
, AUDIO
, OSC
, PLLA_OUT
, PLLM_OUT1
, AUDIO_SYNC
, OSC
),
322 PIN(CDEV2
, AUDIO
, OSC
, AHB_CLK
, APB_CLK
, PLLP_OUT4
, OSC
),
323 PIN(CSUS
, VI
, PLLC_OUT1
, PLLP_OUT2
, PLLP_OUT3
, VI_SENSOR_CLK
,
325 PIN(DAP1
, AUDIO
, DAP1
, RSVD
, GMI
, SDIO2
, DAP1
),
327 PIN(DAP2
, AUDIO
, DAP2
, TWC
, RSVD
, GMI
, DAP2
),
328 PIN(DAP3
, BB
, DAP3
, RSVD
, RSVD
, RSVD
, DAP3
),
329 PIN(DAP4
, UART
, DAP4
, RSVD
, GMI
, RSVD
, DAP4
),
330 PIN(DTA
, VI
, RSVD
, SDIO2
, VI
, RSVD
, RSVD4
),
331 PIN(DTB
, VI
, RSVD
, RSVD
, VI
, SPI1
, RSVD1
),
332 PIN(DTC
, VI
, RSVD
, RSVD
, VI
, RSVD
, RSVD1
),
333 PIN(DTD
, VI
, RSVD
, SDIO2
, VI
, RSVD
, RSVD1
),
334 PIN(DTE
, VI
, RSVD
, RSVD
, VI
, SPI1
, RSVD1
),
336 PINP(GPU
, UART
, PWM
, UARTA
, GMI
, RSVD
, RSVD4
,
338 PIN(GPV
, SD
, PCIE
, RSVD
, RSVD
, RSVD
, PCIE
),
339 PIN(I2CP
, SYS
, I2C
, RSVD
, RSVD
, RSVD
, RSVD4
),
340 PIN(IRTX
, UART
, UARTA
, UARTB
, GMI
, SPI4
, UARTB
),
341 PIN(IRRX
, UART
, UARTA
, UARTB
, GMI
, SPI4
, UARTB
),
342 PIN(KBCB
, SYS
, KBC
, NAND
, SDIO2
, MIO
, KBC
),
343 PIN(KBCA
, SYS
, KBC
, NAND
, SDIO2
, EMC_TEST0_DLL
, KBC
),
344 PINP(PMC
, SYS
, PWR_ON
, PWR_INTR
, RSVD
, RSVD
, PWR_ON
, NONE
),
346 PIN(PTA
, NAND
, I2C2
, HDMI
, GMI
, RSVD
, RSVD4
),
347 PIN(RM
, UART
, I2C
, RSVD
, RSVD
, RSVD
, RSVD4
),
348 PIN(KBCE
, SYS
, KBC
, NAND
, OWR
, RSVD
, KBC
),
349 PIN(KBCF
, SYS
, KBC
, NAND
, TRACE
, MIO
, KBC
),
350 PIN(GMA
, NAND
, UARTE
, SPI3
, GMI
, SDIO4
, SPI3
),
351 PIN(GMC
, NAND
, UARTD
, SPI4
, GMI
, SFLASH
, SPI4
),
352 PIN(SDMMC1
, BB
, SDIO1
, RSVD
, UARTE
, UARTA
, RSVD2
),
353 PIN(OWC
, SYS
, OWR
, RSVD
, RSVD
, RSVD
, OWR
),
355 PIN(GME
, NAND
, RSVD
, DAP5
, GMI
, SDIO4
, GMI
),
356 PIN(SDC
, SD
, PWM
, TWC
, SDIO3
, SPI3
, TWC
),
357 PIN(SDD
, SD
, UARTA
, PWM
, SDIO3
, SPI3
, PWM
),
359 PINP(SLXA
, SD
, PCIE
, SPI4
, SDIO3
, SPI2
, PCIE
, CRTP
),
360 PIN(SLXC
, SD
, SPDIF
, SPI4
, SDIO3
, SPI2
, SPI4
),
361 PIN(SLXD
, SD
, SPDIF
, SPI4
, SDIO3
, SPI2
, SPI4
),
362 PIN(SLXK
, SD
, PCIE
, SPI4
, SDIO3
, SPI2
, PCIE
),
364 PIN(SPDI
, AUDIO
, SPDIF
, RSVD
, I2C
, SDIO2
, RSVD2
),
365 PIN(SPDO
, AUDIO
, SPDIF
, RSVD
, I2C
, SDIO2
, RSVD2
),
366 PIN(SPIA
, AUDIO
, SPI1
, SPI2
, SPI3
, GMI
, GMI
),
367 PIN(SPIB
, AUDIO
, SPI1
, SPI2
, SPI3
, GMI
, GMI
),
368 PIN(SPIC
, AUDIO
, SPI1
, SPI2
, SPI3
, GMI
, GMI
),
369 PIN(SPID
, AUDIO
, SPI2
, SPI1
, SPI2_ALT
, GMI
, GMI
),
370 PIN(SPIE
, AUDIO
, SPI2
, SPI1
, SPI2_ALT
, GMI
, GMI
),
371 PIN(SPIF
, AUDIO
, SPI3
, SPI1
, SPI2
, RSVD
, RSVD4
),
373 PIN(SPIG
, AUDIO
, SPI3
, SPI2
, SPI2_ALT
, I2C
, SPI2_ALT
),
374 PIN(SPIH
, AUDIO
, SPI3
, SPI2
, SPI2_ALT
, I2C
, SPI2_ALT
),
375 PIN(UAA
, BB
, SPI3
, MIPI_HS
, UARTA
, ULPI
, MIPI_HS
),
376 PIN(UAB
, BB
, SPI2
, MIPI_HS
, UARTA
, ULPI
, MIPI_HS
),
377 PIN(UAC
, BB
, OWR
, RSVD
, RSVD
, RSVD
, RSVD4
),
378 PIN(UAD
, UART
, UARTB
, SPDIF
, UARTA
, SPI4
, SPDIF
),
379 PIN(UCA
, UART
, UARTC
, RSVD
, GMI
, RSVD
, RSVD4
),
380 PIN(UCB
, UART
, UARTC
, PWM
, GMI
, RSVD
, RSVD4
),
383 PIN(ATE
, NAND
, IDE
, NAND
, GMI
, RSVD
, IDE
),
384 PIN(KBCC
, SYS
, KBC
, NAND
, TRACE
, EMC_TEST1_DLL
, KBC
),
387 PIN(GMB
, NAND
, IDE
, NAND
, GMI
, GMI_INT
, GMI
),
388 PIN(GMD
, NAND
, RSVD
, NAND
, GMI
, SFLASH
, GMI
),
389 PIN(DDC
, LCD
, I2C2
, RSVD
, RSVD
, RSVD
, RSVD4
),
392 PINP(LD0
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
393 PINP(LD1
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
394 PINP(LD2
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
395 PINP(LD3
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
396 PINP(LD4
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
397 PINP(LD5
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
398 PINP(LD6
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
399 PINP(LD7
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
401 PINP(LD8
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
402 PINP(LD9
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
403 PINP(LD10
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
404 PINP(LD11
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
405 PINP(LD12
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
406 PINP(LD13
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
407 PINP(LD14
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
408 PINP(LD15
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
410 PINP(LD16
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LD17
),
411 PINP(LD17
, LCD
, DISPA
, DISPB
, RSVD
, RSVD
, RSVD4
, LD17
),
412 PINP(LHP0
, LCD
, DISPA
, DISPB
, RSVD
, RSVD
, RSVD4
, LD21_20
),
413 PINP(LHP1
, LCD
, DISPA
, DISPB
, RSVD
, RSVD
, RSVD4
, LD19_18
),
414 PINP(LHP2
, LCD
, DISPA
, DISPB
, RSVD
, RSVD
, RSVD4
, LD19_18
),
415 PINP(LVP0
, LCD
, DISPA
, DISPB
, RSVD
, RSVD
, RSVD4
, LC
),
416 PINP(LVP1
, LCD
, DISPA
, DISPB
, RSVD
, RSVD
, RSVD4
, LD21_20
),
417 PINP(HDINT
, LCD
, HDMI
, RSVD
, RSVD
, RSVD
, HDMI
, LC
),
419 PINP(LM0
, LCD
, DISPA
, DISPB
, SPI3
, RSVD
, RSVD4
, LC
),
420 PINP(LM1
, LCD
, DISPA
, DISPB
, RSVD
, CRT
, RSVD3
, LC
),
421 PINP(LVS
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LC
),
422 PINP(LSC0
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LC
),
423 PINP(LSC1
, LCD
, DISPA
, DISPB
, SPI3
, HDMI
, DISPA
, LS
),
424 PINP(LSCK
, LCD
, DISPA
, DISPB
, SPI3
, HDMI
, DISPA
, LS
),
425 PINP(LDC
, LCD
, DISPA
, DISPB
, RSVD
, RSVD
, RSVD4
, LS
),
426 PINP(LCSN
, LCD
, DISPA
, DISPB
, SPI3
, RSVD
, RSVD4
, LS
),
429 PINP(LSPI
, LCD
, DISPA
, DISPB
, XIO
, HDMI
, DISPA
, LC
),
430 PINP(LSDA
, LCD
, DISPA
, DISPB
, SPI3
, HDMI
, DISPA
, LS
),
431 PINP(LSDI
, LCD
, DISPA
, DISPB
, SPI3
, RSVD
, DISPA
, LS
),
432 PINP(LPW0
, LCD
, DISPA
, DISPB
, SPI3
, HDMI
, DISPA
, LS
),
433 PINP(LPW1
, LCD
, DISPA
, DISPB
, RSVD
, RSVD
, RSVD4
, LS
),
434 PINP(LPW2
, LCD
, DISPA
, DISPB
, SPI3
, HDMI
, DISPA
, LS
),
435 PINP(LDI
, LCD
, DISPA
, DISPB
, RSVD
, RSVD
, RSVD4
, LD23_22
),
436 PINP(LHS
, LCD
, DISPA
, DISPB
, XIO
, RSVD
, RSVD4
, LC
),
438 PINP(LPP
, LCD
, DISPA
, DISPB
, RSVD
, RSVD
, RSVD4
, LD23_22
),
440 PIN(KBCD
, SYS
, KBC
, NAND
, SDIO2
, MIO
, KBC
),
441 PIN(GPU7
, SYS
, RTCK
, RSVD
, RSVD
, RSVD
, RTCK
),
442 PIN(DTF
, VI
, I2C3
, RSVD
, VI
, RSVD
, RSVD4
),
443 PIN(UDA
, BB
, SPI1
, RSVD
, UARTD
, ULPI
, RSVD2
),
444 PIN(CRTP
, LCD
, CRT
, RSVD
, RSVD
, RSVD
, RSVD
),
445 PINP(SDB
, SD
, UARTA
, PWM
, SDIO3
, SPI2
, PWM
, NONE
),
447 /* these pin groups only have pullup and pull down control */
448 PINALL(CK32
, SYS
, RSVD
, RSVD
, RSVD
, RSVD
, RSVD
, MUXCTL_NONE
,
450 PINALL(DDRC
, DDR
, RSVD
, RSVD
, RSVD
, RSVD
, RSVD
, MUXCTL_NONE
,
452 PINALL(PMCA
, SYS
, RSVD
, RSVD
, RSVD
, RSVD
, RSVD
, MUXCTL_NONE
,
454 PINALL(PMCB
, SYS
, RSVD
, RSVD
, RSVD
, RSVD
, RSVD
, MUXCTL_NONE
,
456 PINALL(PMCC
, SYS
, RSVD
, RSVD
, RSVD
, RSVD
, RSVD
, MUXCTL_NONE
,
458 PINALL(PMCD
, SYS
, RSVD
, RSVD
, RSVD
, RSVD
, RSVD
, MUXCTL_NONE
,
460 PINALL(PMCE
, SYS
, RSVD
, RSVD
, RSVD
, RSVD
, RSVD
, MUXCTL_NONE
,
462 PINALL(XM2C
, DDR
, RSVD
, RSVD
, RSVD
, RSVD
, RSVD
, MUXCTL_NONE
,
464 PINALL(XM2D
, DDR
, RSVD
, RSVD
, RSVD
, RSVD
, RSVD
, MUXCTL_NONE
,
468 void pinmux_set_tristate(enum pmux_pingrp pin
, int enable
)
470 struct pmux_tri_ctlr
*pmt
=
471 (struct pmux_tri_ctlr
*)NV_PA_APB_MISC_BASE
;
472 u32
*tri
= &pmt
->pmt_tri
[TRISTATE_REG(pin
)];
477 reg
|= TRISTATE_MASK(pin
);
479 reg
&= ~TRISTATE_MASK(pin
);
483 void pinmux_tristate_enable(enum pmux_pingrp pin
)
485 pinmux_set_tristate(pin
, 1);
488 void pinmux_tristate_disable(enum pmux_pingrp pin
)
490 pinmux_set_tristate(pin
, 0);
493 void pinmux_set_pullupdown(enum pmux_pingrp pin
, enum pmux_pull pupd
)
495 struct pmux_tri_ctlr
*pmt
=
496 (struct pmux_tri_ctlr
*)NV_PA_APB_MISC_BASE
;
497 enum pmux_pullid pull_id
= tegra_soc_pingroups
[pin
].pull_id
;
498 u32
*pull
= &pmt
->pmt_pull
[PULL_REG(pull_id
)];
501 mask_bit
= PULL_SHIFT(pull_id
);
504 reg
&= ~(0x3 << mask_bit
);
505 reg
|= pupd
<< mask_bit
;
509 void pinmux_set_func(enum pmux_pingrp pin
, enum pmux_func func
)
511 struct pmux_tri_ctlr
*pmt
=
512 (struct pmux_tri_ctlr
*)NV_PA_APB_MISC_BASE
;
513 enum pmux_ctlid mux_id
= tegra_soc_pingroups
[pin
].ctl_id
;
514 u32
*muxctl
= &pmt
->pmt_ctl
[MUXCTL_REG(mux_id
)];
519 assert(pmux_func_isvalid(func
));
521 /* Handle special values */
522 if (func
>= PMUX_FUNC_RSVD1
) {
523 mux
= (func
- PMUX_FUNC_RSVD1
) & 0x3;
525 /* Search for the appropriate function */
526 for (i
= 0; i
< 4; i
++) {
527 if (tegra_soc_pingroups
[pin
].funcs
[i
] == func
) {
535 mask_bit
= MUXCTL_SHIFT(mux_id
);
537 reg
&= ~(0x3 << mask_bit
);
538 reg
|= mux
<< mask_bit
;
542 void pinmux_config_pingroup(const struct pingroup_config
*config
)
544 enum pmux_pingrp pin
= config
->pingroup
;
546 pinmux_set_func(pin
, config
->func
);
547 pinmux_set_pullupdown(pin
, config
->pull
);
548 pinmux_set_tristate(pin
, config
->tristate
);
551 void pinmux_config_table(const struct pingroup_config
*config
, int len
)
555 for (i
= 0; i
< len
; i
++)
556 pinmux_config_pingroup(&config
[i
]);