2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 /* Tegra30 Clock control functions */
21 #include <asm/arch/clock.h>
22 #include <asm/arch/tegra.h>
23 #include <asm/arch-tegra/clk_rst.h>
24 #include <asm/arch-tegra/timer.h>
29 * Clock types that we can use as a source. The Tegra30 has muxes for the
30 * peripheral clocks, and in most cases there are four options for the clock
31 * source. This gives us a clock 'type' and exploits what commonality exists
34 * Letters are obvious, except for T which means CLK_M, and S which means the
35 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
36 * datasheet) and PLL_M are different things. The former is the basic
37 * clock supplied to the SOC from an external oscillator. The latter is the
40 * See definitions in clock_id in the header file.
43 CLOCK_TYPE_AXPT
, /* PLL_A, PLL_X, PLL_P, CLK_M */
44 CLOCK_TYPE_MCPA
, /* and so on */
56 CLOCK_TYPE_NONE
= -1, /* invalid clock type */
60 CLOCK_MAX_MUX
= 8 /* number of source options for each clock */
64 MASK_BITS_31_30
= 2, /* num of bits used to specify clock source */
70 * Clock source mux for each clock type. This just converts our enum into
71 * a list of mux sources for use by the code.
74 * The extra column in each clock source array is used to store the mask
75 * bits in its register for the source.
77 #define CLK(x) CLOCK_ID_ ## x
78 static enum clock_id clock_source
[CLOCK_TYPE_COUNT
][CLOCK_MAX_MUX
+1] = {
79 { CLK(AUDIO
), CLK(XCPU
), CLK(PERIPH
), CLK(OSC
),
80 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
82 { CLK(MEMORY
), CLK(CGENERAL
), CLK(PERIPH
), CLK(AUDIO
),
83 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
85 { CLK(MEMORY
), CLK(CGENERAL
), CLK(PERIPH
), CLK(OSC
),
86 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
88 { CLK(PERIPH
), CLK(CGENERAL
), CLK(MEMORY
), CLK(NONE
),
89 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
91 { CLK(PERIPH
), CLK(CGENERAL
), CLK(MEMORY
), CLK(OSC
),
92 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
94 { CLK(PERIPH
), CLK(CGENERAL
), CLK(MEMORY
), CLK(OSC
),
95 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
97 { CLK(PERIPH
), CLK(DISPLAY
), CLK(CGENERAL
), CLK(OSC
),
98 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
100 { CLK(AUDIO
), CLK(CGENERAL
), CLK(PERIPH
), CLK(OSC
),
101 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
103 { CLK(AUDIO
), CLK(SFROM32KHZ
), CLK(PERIPH
), CLK(OSC
),
104 CLK(EPCI
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
106 { CLK(PERIPH
), CLK(MEMORY
), CLK(DISPLAY
), CLK(AUDIO
),
107 CLK(CGENERAL
), CLK(DISPLAY2
), CLK(OSC
), CLK(NONE
),
109 { CLK(PERIPH
), CLK(CGENERAL
), CLK(SFROM32KHZ
), CLK(OSC
),
110 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
115 * Clock type for each peripheral clock source. We put the name in each
116 * record just so it is easy to match things up
118 #define TYPE(name, type) type
119 static enum clock_type_id clock_periph_type
[PERIPHC_COUNT
] = {
121 TYPE(PERIPHC_I2S1
, CLOCK_TYPE_AXPT
),
122 TYPE(PERIPHC_I2S2
, CLOCK_TYPE_AXPT
),
123 TYPE(PERIPHC_SPDIF_OUT
, CLOCK_TYPE_AXPT
),
124 TYPE(PERIPHC_SPDIF_IN
, CLOCK_TYPE_PCM
),
125 TYPE(PERIPHC_PWM
, CLOCK_TYPE_PCST
), /* only PWM uses b29:28 */
126 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
127 TYPE(PERIPHC_SBC2
, CLOCK_TYPE_PCMT
),
128 TYPE(PERIPHC_SBC3
, CLOCK_TYPE_PCMT
),
131 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
132 TYPE(PERIPHC_I2C1
, CLOCK_TYPE_PCMT16
),
133 TYPE(PERIPHC_DVC_I2C
, CLOCK_TYPE_PCMT16
),
134 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
135 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
136 TYPE(PERIPHC_SBC1
, CLOCK_TYPE_PCMT
),
137 TYPE(PERIPHC_DISP1
, CLOCK_TYPE_PMDACD2T
),
138 TYPE(PERIPHC_DISP2
, CLOCK_TYPE_PMDACD2T
),
141 TYPE(PERIPHC_CVE
, CLOCK_TYPE_PDCT
),
142 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
143 TYPE(PERIPHC_VI
, CLOCK_TYPE_MCPA
),
144 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
145 TYPE(PERIPHC_SDMMC1
, CLOCK_TYPE_PCMT
),
146 TYPE(PERIPHC_SDMMC2
, CLOCK_TYPE_PCMT
),
147 TYPE(PERIPHC_G3D
, CLOCK_TYPE_MCPA
),
148 TYPE(PERIPHC_G2D
, CLOCK_TYPE_MCPA
),
151 TYPE(PERIPHC_NDFLASH
, CLOCK_TYPE_PCMT
),
152 TYPE(PERIPHC_SDMMC4
, CLOCK_TYPE_PCMT
),
153 TYPE(PERIPHC_VFIR
, CLOCK_TYPE_PCMT
),
154 TYPE(PERIPHC_EPP
, CLOCK_TYPE_MCPA
),
155 TYPE(PERIPHC_MPE
, CLOCK_TYPE_MCPA
),
156 TYPE(PERIPHC_MIPI
, CLOCK_TYPE_PCMT
), /* MIPI base-band HSI */
157 TYPE(PERIPHC_UART1
, CLOCK_TYPE_PCMT
),
158 TYPE(PERIPHC_UART2
, CLOCK_TYPE_PCMT
),
161 TYPE(PERIPHC_HOST1X
, CLOCK_TYPE_MCPA
),
162 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
163 TYPE(PERIPHC_TVO
, CLOCK_TYPE_PDCT
),
164 TYPE(PERIPHC_HDMI
, CLOCK_TYPE_PMDACD2T
),
165 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
166 TYPE(PERIPHC_TVDAC
, CLOCK_TYPE_PDCT
),
167 TYPE(PERIPHC_I2C2
, CLOCK_TYPE_PCMT16
),
168 TYPE(PERIPHC_EMC
, CLOCK_TYPE_MCPT
),
171 TYPE(PERIPHC_UART3
, CLOCK_TYPE_PCMT
),
172 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
173 TYPE(PERIPHC_VI
, CLOCK_TYPE_MCPA
),
174 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
175 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
176 TYPE(PERIPHC_SBC4
, CLOCK_TYPE_PCMT
),
177 TYPE(PERIPHC_I2C3
, CLOCK_TYPE_PCMT16
),
178 TYPE(PERIPHC_SDMMC3
, CLOCK_TYPE_PCMT
),
181 TYPE(PERIPHC_UART4
, CLOCK_TYPE_PCMT
),
182 TYPE(PERIPHC_UART5
, CLOCK_TYPE_PCMT
),
183 TYPE(PERIPHC_VDE
, CLOCK_TYPE_PCMT
),
184 TYPE(PERIPHC_OWR
, CLOCK_TYPE_PCMT
),
185 TYPE(PERIPHC_NOR
, CLOCK_TYPE_PCMT
),
186 TYPE(PERIPHC_CSITE
, CLOCK_TYPE_PCMT
),
187 TYPE(PERIPHC_I2S0
, CLOCK_TYPE_AXPT
),
188 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
190 /* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
191 TYPE(PERIPHC_G3D2
, CLOCK_TYPE_MCPA
),
192 TYPE(PERIPHC_MSELECT
, CLOCK_TYPE_PCMT
),
193 TYPE(PERIPHC_TSENSOR
, CLOCK_TYPE_PCST
), /* s/b PCTS */
194 TYPE(PERIPHC_I2S3
, CLOCK_TYPE_AXPT
),
195 TYPE(PERIPHC_I2S4
, CLOCK_TYPE_AXPT
),
196 TYPE(PERIPHC_I2C4
, CLOCK_TYPE_PCMT16
),
197 TYPE(PERIPHC_SBC5
, CLOCK_TYPE_PCMT
),
198 TYPE(PERIPHC_SBC6
, CLOCK_TYPE_PCMT
),
201 TYPE(PERIPHC_AUDIO
, CLOCK_TYPE_ACPT
),
202 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
203 TYPE(PERIPHC_DAM0
, CLOCK_TYPE_ACPT
),
204 TYPE(PERIPHC_DAM1
, CLOCK_TYPE_ACPT
),
205 TYPE(PERIPHC_DAM2
, CLOCK_TYPE_ACPT
),
206 TYPE(PERIPHC_HDA2CODEC2X
, CLOCK_TYPE_PCMT
),
207 TYPE(PERIPHC_ACTMON
, CLOCK_TYPE_PCST
), /* MASK 31:30 */
208 TYPE(PERIPHC_EXTPERIPH1
, CLOCK_TYPE_ASPTE
),
211 TYPE(PERIPHC_EXTPERIPH2
, CLOCK_TYPE_ASPTE
),
212 TYPE(PERIPHC_EXTPERIPH3
, CLOCK_TYPE_ASPTE
),
213 TYPE(PERIPHC_NANDSPEED
, CLOCK_TYPE_PCMT
),
214 TYPE(PERIPHC_I2CSLOW
, CLOCK_TYPE_PCST
), /* MASK 31:30 */
215 TYPE(PERIPHC_SYS
, CLOCK_TYPE_NONE
),
216 TYPE(PERIPHC_SPEEDO
, CLOCK_TYPE_PCMT
),
217 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
218 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
221 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
222 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
223 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
224 TYPE(PERIPHC_NONE
, CLOCK_TYPE_NONE
),
225 TYPE(PERIPHC_SATAOOB
, CLOCK_TYPE_PCMT
), /* offset 0x420h */
226 TYPE(PERIPHC_SATA
, CLOCK_TYPE_PCMT
),
227 TYPE(PERIPHC_HDA
, CLOCK_TYPE_PCMT
),
231 * This array translates a periph_id to a periphc_internal_id
233 * Not present/matched up:
234 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
235 * SPDIF - which is both 0x08 and 0x0c
238 #define NONE(name) (-1)
239 #define OFFSET(name, value) PERIPHC_ ## name
240 static s8 periph_id_to_internal_id
[PERIPH_ID_COUNT
] = {
249 PERIPHC_UART2
, /* and vfir 0x68 */
254 NONE(SPDIF
), /* 0x08 and 0x0c, unclear which to use */
281 /* Middle word: 63:32 */
293 NONE(SBC1
), /* SBC1, 0x34, is this SPI1? */
303 PERIPHC_TVO
, /* also CVE 0x40 */
321 /* Upper word 95:64 */
404 NONE(RESERVED0_PCIERX0
),
405 NONE(RESERVED1_PCIERX1
),
406 NONE(RESERVED2_PCIERX2
),
407 NONE(RESERVED3_PCIERX3
),
408 NONE(RESERVED4_PCIERX4
),
409 NONE(RESERVED5_PCIERX5
),
413 NONE(RESERVED6_PCIE2
),
415 NONE(RESERVED8_HDMI
),
416 NONE(RESERVED9_SATA
),
417 NONE(RESERVED10_MIPI
),
423 * Get the oscillator frequency, from the corresponding hardware configuration
424 * field. Note that T30 supports 3 new higher freqs, but we map back
425 * to the old T20 freqs. Support for the higher oscillators is TBD.
427 enum clock_osc_freq
clock_get_osc_freq(void)
429 struct clk_rst_ctlr
*clkrst
=
430 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
433 reg
= readl(&clkrst
->crc_osc_ctrl
);
434 reg
= (reg
& OSC_FREQ_MASK
) >> OSC_FREQ_SHIFT
;
436 if (reg
& 1) /* one of the newer freqs */
437 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg
);
439 return reg
>> 2; /* Map to most common (T20) freqs */
442 /* Returns a pointer to the clock source register for a peripheral */
443 u32
*get_periph_source_reg(enum periph_id periph_id
)
445 struct clk_rst_ctlr
*clkrst
=
446 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
447 enum periphc_internal_id internal_id
;
449 /* Coresight is a special case */
450 if (periph_id
== PERIPH_ID_CSI
)
451 return &clkrst
->crc_clk_src
[PERIPH_ID_CSI
+1];
453 assert(periph_id
>= PERIPH_ID_FIRST
&& periph_id
< PERIPH_ID_COUNT
);
454 internal_id
= periph_id_to_internal_id
[periph_id
];
455 assert(internal_id
!= -1);
456 if (internal_id
>= PERIPHC_VW_FIRST
) {
457 internal_id
-= PERIPHC_VW_FIRST
;
458 return &clkrst
->crc_clk_src_vw
[internal_id
];
460 return &clkrst
->crc_clk_src
[internal_id
];
464 * Given a peripheral ID and the required source clock, this returns which
465 * value should be programmed into the source mux for that peripheral.
467 * There is special code here to handle the one source type with 5 sources.
469 * @param periph_id peripheral to start
470 * @param source PLL id of required parent clock
471 * @param mux_bits Set to number of bits in mux register: 2 or 4
472 * @param divider_bits Set to number of divider bits (8 or 16)
473 * @return mux value (0-4, or -1 if not found)
475 int get_periph_clock_source(enum periph_id periph_id
,
476 enum clock_id parent
, int *mux_bits
, int *divider_bits
)
478 enum clock_type_id type
;
479 enum periphc_internal_id internal_id
;
482 assert(clock_periph_id_isvalid(periph_id
));
484 internal_id
= periph_id_to_internal_id
[periph_id
];
485 assert(periphc_internal_id_isvalid(internal_id
));
487 type
= clock_periph_type
[internal_id
];
488 assert(clock_type_id_isvalid(type
));
490 *mux_bits
= clock_source
[type
][CLOCK_MAX_MUX
];
492 if (type
== CLOCK_TYPE_PCMT16
)
497 for (mux
= 0; mux
< CLOCK_MAX_MUX
; mux
++)
498 if (clock_source
[type
][mux
] == parent
)
501 /* if we get here, either us or the caller has made a mistake */
502 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id
,
507 void clock_set_enable(enum periph_id periph_id
, int enable
)
509 struct clk_rst_ctlr
*clkrst
=
510 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
514 /* Enable/disable the clock to this peripheral */
515 assert(clock_periph_id_isvalid(periph_id
));
516 if ((int)periph_id
< (int)PERIPH_ID_VW_FIRST
)
517 clk
= &clkrst
->crc_clk_out_enb
[PERIPH_REG(periph_id
)];
519 clk
= &clkrst
->crc_clk_out_enb_vw
[PERIPH_REG(periph_id
)];
522 reg
|= PERIPH_MASK(periph_id
);
524 reg
&= ~PERIPH_MASK(periph_id
);
528 void reset_set_enable(enum periph_id periph_id
, int enable
)
530 struct clk_rst_ctlr
*clkrst
=
531 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
535 /* Enable/disable reset to the peripheral */
536 assert(clock_periph_id_isvalid(periph_id
));
537 if (periph_id
< PERIPH_ID_VW_FIRST
)
538 reset
= &clkrst
->crc_rst_dev
[PERIPH_REG(periph_id
)];
540 reset
= &clkrst
->crc_rst_dev_vw
[PERIPH_REG(periph_id
)];
543 reg
|= PERIPH_MASK(periph_id
);
545 reg
&= ~PERIPH_MASK(periph_id
);
549 #ifdef CONFIG_OF_CONTROL
551 * Convert a device tree clock ID to our peripheral ID. They are mostly
552 * the same but we are very cautious so we check that a valid clock ID is
555 * @param clk_id Clock ID according to tegra30 device tree binding
556 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
558 enum periph_id
clk_id_to_periph_id(int clk_id
)
560 if (clk_id
> PERIPH_ID_COUNT
)
561 return PERIPH_ID_NONE
;
564 case PERIPH_ID_RESERVED3
:
565 case PERIPH_ID_RESERVED4
:
566 case PERIPH_ID_RESERVED16
:
567 case PERIPH_ID_RESERVED24
:
568 case PERIPH_ID_RESERVED35
:
569 case PERIPH_ID_RESERVED43
:
570 case PERIPH_ID_RESERVED45
:
571 case PERIPH_ID_RESERVED56
:
572 case PERIPH_ID_RESERVED76
:
573 case PERIPH_ID_RESERVED77
:
574 case PERIPH_ID_RESERVED78
:
575 case PERIPH_ID_RESERVED83
:
576 case PERIPH_ID_RESERVED89
:
577 case PERIPH_ID_RESERVED91
:
578 case PERIPH_ID_RESERVED93
:
579 case PERIPH_ID_RESERVED94
:
580 case PERIPH_ID_RESERVED95
:
581 return PERIPH_ID_NONE
;
586 #endif /* CONFIG_OF_CONTROL */
588 void clock_early_init(void)
591 * PLLP output frequency set to 408Mhz
592 * PLLC output frequency set to 228Mhz
594 switch (clock_get_osc_freq()) {
595 case CLOCK_OSC_FREQ_12_0
: /* OSC is 12Mhz */
596 clock_set_rate(CLOCK_ID_PERIPH
, 408, 12, 0, 8);
597 clock_set_rate(CLOCK_ID_CGENERAL
, 456, 12, 1, 8);
600 case CLOCK_OSC_FREQ_26_0
: /* OSC is 26Mhz */
601 clock_set_rate(CLOCK_ID_PERIPH
, 408, 26, 0, 8);
602 clock_set_rate(CLOCK_ID_CGENERAL
, 600, 26, 0, 8);
605 case CLOCK_OSC_FREQ_13_0
: /* OSC is 13Mhz */
606 clock_set_rate(CLOCK_ID_PERIPH
, 408, 13, 0, 8);
607 clock_set_rate(CLOCK_ID_CGENERAL
, 600, 13, 0, 8);
609 case CLOCK_OSC_FREQ_19_2
:
612 * These are not supported. It is too early to print a
613 * message and the UART likely won't work anyway due to the
614 * oscillator being wrong.