arch/arm/dts/fsl-ls2080a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP ls2080a SOC common device tree source
   4  *
   5  * Copyright 2020-2021 NXP
   6  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   7  */
   8
   9 / {
  10         compatible = "fsl,ls2080a";
  11         interrupt-parent = <&gic>;
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         memory@80000000 {
  16                 device_type = "memory";
  17                 reg = <0x00000000 0x80000000 0 0x80000000>;
  18                       /* DRAM space - 1, size : 2 GB DRAM */
  19         };
  20
  21         gic: interrupt-controller@6000000 {
  22                 compatible = "arm,gic-v3";
  23                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  24                       <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
  25                 #interrupt-cells = <3>;
  26                 interrupt-controller;
  27                 interrupts = <1 9 0x4>;
  28         };
  29
  30         timer {
  31                 compatible = "arm,armv8-timer";
  32                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  33                              <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  34                              <1 11 0x8>, /* Virtual PPI, active-low */
  35                              <1 10 0x8>; /* Hypervisor PPI, active-low */
  36         };
  37
  38         serial0: serial@21c0500 {
  39                 device_type = "serial";
  40                 compatible = "fsl,ns16550", "ns16550a";
  41                 reg = <0x0 0x21c0500 0x0 0x100>;
  42                 clock-frequency = <0>;  /* Updated by bootloader */
  43                 interrupts = <0 32 0x1>; /* edge triggered */
  44         };
  45
  46         serial1: serial@21c0600 {
  47                 device_type = "serial";
  48                 compatible = "fsl,ns16550", "ns16550a";
  49                 reg = <0x0 0x21c0600 0x0 0x100>;
  50                 clock-frequency = <0>;  /* Updated by bootloader */
  51                 interrupts = <0 32 0x1>; /* edge triggered */
  52         };
  53
  54         i2c0: i2c@2000000 {
  55                 status = "disabled";
  56                 compatible = "fsl,vf610-i2c";
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59                 reg = <0x0 0x2000000 0x0 0x10000>;
  60                 interrupts = <0 34 0x4>; /* Level high type */
  61         };
  62
  63         i2c1: i2c@2010000 {
  64                 status = "disabled";
  65                 compatible = "fsl,vf610-i2c";
  66                 #address-cells = <1>;
  67                 #size-cells = <0>;
  68                 reg = <0x0 0x2010000 0x0 0x10000>;
  69                 interrupts = <0 34 0x4>; /* Level high type */
  70         };
  71
  72         i2c2: i2c@2020000 {
  73                 status = "disabled";
  74                 compatible = "fsl,vf610-i2c";
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77                 reg = <0x0 0x2020000 0x0 0x10000>;
  78                 interrupts = <0 35 0x4>; /* Level high type */
  79         };
  80
  81         i2c3: i2c@2030000 {
  82                 status = "disabled";
  83                 compatible = "fsl,vf610-i2c";
  84                 #address-cells = <1>;
  85                 #size-cells = <0>;
  86                 reg = <0x0 0x2030000 0x0 0x10000>;
  87                 interrupts = <0 35 0x4>; /* Level high type */
  88         };
  89
  90         dspi: dspi@2100000 {
  91                 compatible = "fsl,vf610-dspi";
  92                 #address-cells = <1>;
  93                 #size-cells = <0>;
  94                 reg = <0x0 0x2100000 0x0 0x10000>;
  95                 interrupts = <0 26 0x4>; /* Level high type */
  96                 spi-num-chipselects = <6>;
  97         };
  98
  99         qspi: quadspi@1550000 {
 100                 compatible = "fsl,ls2080a-qspi";
 101                 #address-cells = <1>;
 102                 #size-cells = <0>;
 103                 reg = <0x0 0x20c0000 0x0 0x10000>,
 104                         <0x0 0x20000000 0x0 0x10000000>;
 105                 reg-names = "QuadSPI", "QuadSPI-memory";
 106                 status = "disabled";
 107         };
 108
 109         esdhc: esdhc@0 {
 110                 compatible = "fsl,esdhc";
 111                 reg = <0x0 0x2140000 0x0 0x10000>;
 112                 interrupts = <0 28 0x4>; /* Level high type */
 113                 little-endian;
 114                 bus-width = <4>;
 115         };
 116
 117         gpio0: gpio@2300000 {
 118                 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 119                 reg = <0x0 0x2300000 0x0 0x10000>;
 120                 interrupts = <0 36 0x4>; /* Level high type */
 121                 gpio-controller;
 122                 little-endian;
 123                 #gpio-cells = <2>;
 124                 interrupt-controller;
 125                 #interrupt-cells = <2>;
 126         };
 127
 128         gpio1: gpio@2310000 {
 129                 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 130                 reg = <0x0 0x2310000 0x0 0x10000>;
 131                 interrupts = <0 36 0x4>; /* Level high type */
 132                 gpio-controller;
 133                 little-endian;
 134                 #gpio-cells = <2>;
 135                 interrupt-controller;
 136                 #interrupt-cells = <2>;
 137         };
 138
 139         gpio2: gpio@2320000 {
 140                 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 141                 reg = <0x0 0x2320000 0x0 0x10000>;
 142                 interrupts = <0 37 0x4>; /* Level high type */
 143                 gpio-controller;
 144                 little-endian;
 145                 #gpio-cells = <2>;
 146                 interrupt-controller;
 147                 #interrupt-cells = <2>;
 148         };
 149
 150         gpio3: gpio@2330000 {
 151                 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 152                 reg = <0x0 0x2330000 0x0 0x10000>;
 153                 interrupts = <0 37 0x4>; /* Level high type */
 154                 gpio-controller;
 155                 little-endian;
 156                 #gpio-cells = <2>;
 157                 interrupt-controller;
 158                 #interrupt-cells = <2>;
 159         };
 160
 161         usb0: usb3@3100000 {
 162                 compatible = "fsl,layerscape-dwc3";
 163                 reg = <0x0 0x3100000 0x0 0x10000>;
 164                 interrupts = <0 80 0x4>; /* Level high type */
 165                 dr_mode = "host";
 166         };
 167
 168         usb1: usb3@3110000 {
 169                 compatible = "fsl,layerscape-dwc3";
 170                 reg = <0x0 0x3110000 0x0 0x10000>;
 171                 interrupts = <0 81 0x4>; /* Level high type */
 172                 dr_mode = "host";
 173         };
 174
 175         pcie1: pcie@3400000 {
 176                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 177                 reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 178                        0x00 0x03480000 0x0 0x80000   /* lut registers */
 179                        0x10 0x00000000 0x0 0x20000>; /* configuration space */
 180                 reg-names = "dbi", "lut", "config";
 181                 #address-cells = <3>;
 182                 #size-cells = <2>;
 183                 device_type = "pci";
 184                 num-lanes = <4>;
 185                 bus-range = <0x0 0xff>;
 186                 ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000   /* downstream I/O */
 187                           0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 188         };
 189
 190         pcie2: pcie@3500000 {
 191                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 192                 reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 193                        0x00 0x03580000 0x0 0x80000   /* lut registers */
 194                        0x12 0x00000000 0x0 0x20000>; /* configuration space */
 195                 reg-names = "dbi", "lut", "config";
 196                 #address-cells = <3>;
 197                 #size-cells = <2>;
 198                 device_type = "pci";
 199                 num-lanes = <4>;
 200                 bus-range = <0x0 0xff>;
 201                 ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000   /* downstream I/O */
 202                           0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 203         };
 204
 205         pcie3: pcie@3600000 {
 206                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 207                 reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 208                        0x00 0x03680000 0x0 0x80000   /* lut registers */
 209                        0x14 0x00000000 0x0 0x20000>; /* configuration space */
 210                 reg-names = "dbi", "lut", "config";
 211                 #address-cells = <3>;
 212                 #size-cells = <2>;
 213                 device_type = "pci";
 214                 num-lanes = <8>;
 215                 bus-range = <0x0 0xff>;
 216                 ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000   /* downstream I/O */
 217                           0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 218         };
 219
 220         pcie4: pcie@3700000 {
 221                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 222                 reg = <0x00 0x03700000 0x0 0x80000   /* dbi registers */
 223                        0x00 0x03780000 0x0 0x80000   /* lut registers */
 224                        0x16 0x00000000 0x0 0x20000>; /* configuration space */
 225                 reg-names = "dbi", "lut", "config";
 226                 #address-cells = <3>;
 227                 #size-cells = <2>;
 228                 device_type = "pci";
 229                 num-lanes = <4>;
 230                 bus-range = <0x0 0xff>;
 231                 ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000   /* downstream I/O */
 232                           0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 233         };
 234
 235         sata: sata@3200000 {
 236                         compatible = "fsl,ls2080a-ahci";
 237                         reg = <0x0 0x3200000 0x0 0x10000>;
 238                         interrupts = <0 133 0x4>; /* Level high type */
 239                         status = "disabled";
 240         };
 241
 242         crypto: crypto@8000000 {
 243                 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 244                 fsl,sec-era = <8>;
 245                 #address-cells = <1>;
 246                 #size-cells = <1>;
 247                 ranges = <0x0 0x00 0x8000000 0x100000>;
 248                 reg = <0x00 0x8000000 0x0 0x100000>;
 249                 interrupts = <0 139 0x4>;  /* Level high type */
 250                 dma-coherent;
 251
 252                 sec_jr0: jr@10000 {
 253                         compatible = "fsl,sec-v5.0-job-ring",
 254                                      "fsl,sec-v4.0-job-ring";
 255                         reg        = <0x10000 0x10000>;
 256                         interrupts = <0 140 0x4>;  /* Level high type */
 257                 };
 258
 259                 sec_jr1: jr@20000 {
 260                         compatible = "fsl,sec-v5.0-job-ring",
 261                                      "fsl,sec-v4.0-job-ring";
 262                         reg        = <0x20000 0x10000>;
 263                         interrupts = <0 141 0x4>;  /* Level high type */
 264                 };
 265
 266                 sec_jr2: jr@30000 {
 267                         compatible = "fsl,sec-v5.0-job-ring",
 268                                      "fsl,sec-v4.0-job-ring";
 269                         reg        = <0x30000 0x10000>;
 270                         interrupts = <0 142 0x4>;  /* Level high type */
 271                 };
 272
 273                 sec_jr3: jr@40000 {
 274                         compatible = "fsl,sec-v5.0-job-ring",
 275                                      "fsl,sec-v4.0-job-ring";
 276                         reg        = <0x40000 0x10000>;
 277                         interrupts = <0 143 0x4>;  /* Level high type */
 278                 };
 279         };
 280
 281         fsl_mc: fsl-mc@80c000000 {
 282                 compatible = "fsl,qoriq-mc", "simple-mfd";
 283                 reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 284                       <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 285                 #address-cells = <3>;
 286                 #size-cells = <1>;
 287
 288                 /*
 289                  * Region type 0x0 - MC portals
 290                  * Region type 0x1 - QBMAN portals
 291                  */
 292                 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 293                         0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 294
 295                 dpmacs {
 296                         compatible = "simple-mfd";
 297                         #address-cells = <1>;
 298                         #size-cells = <0>;
 299
 300                         dpmac1: dpmac@1 {
 301                                 compatible = "fsl,qoriq-mc-dpmac";
 302                                 reg = <0x1>;
 303                                 status = "disabled";
 304                         };
 305
 306                         dpmac2: dpmac@2 {
 307                                 compatible = "fsl,qoriq-mc-dpmac";
 308                                 reg = <0x2>;
 309                                 status = "disabled";
 310                         };
 311
 312                         dpmac3: dpmac@3 {
 313                                 compatible = "fsl,qoriq-mc-dpmac";
 314                                 reg = <0x3>;
 315                                 status = "disabled";
 316                         };
 317
 318                         dpmac4: dpmac@4 {
 319                                 compatible = "fsl,qoriq-mc-dpmac";
 320                                 reg = <0x4>;
 321                                 status = "disabled";
 322                         };
 323
 324                         dpmac5: dpmac@5 {
 325                                 compatible = "fsl,qoriq-mc-dpmac";
 326                                 reg = <0x5>;
 327                                 status = "disabled";
 328                         };
 329
 330                         dpmac6: dpmac@6 {
 331                                 compatible = "fsl,qoriq-mc-dpmac";
 332                                 reg = <0x6>;
 333                                 status = "disabled";
 334                         };
 335
 336                         dpmac7: dpmac@7 {
 337                                 compatible = "fsl,qoriq-mc-dpmac";
 338                                 reg = <0x7>;
 339                                 status = "disabled";
 340                         };
 341
 342                         dpmac8: dpmac@8 {
 343                                 compatible = "fsl,qoriq-mc-dpmac";
 344                                 reg = <0x8>;
 345                                 status = "disabled";
 346                         };
 347                 };
 348         };
 349
 350         emdio1: mdio@8B96000 {
 351                 compatible = "fsl,ls-mdio";
 352                 reg = <0x0 0x8B96000 0x0 0x1000>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 status = "disabled";
 356         };
 357
 358         emdio2: mdio@8B97000 {
 359                 compatible = "fsl,ls-mdio";
 360                 reg = <0x0 0x8B97000 0x0 0x1000>;
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363                 status = "disabled";
 364         };
 365 };