arch/arm/dts/fsl-ls2080a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP ls2080a SOC common device tree source
   4  *
   5  * Copyright 2020-2021 NXP
   6  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   7  */
   8
   9 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
  10
  11 / {
  12         compatible = "fsl,ls2080a";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         aliases {
  18                 serial0 = &serial0;
  19                 serial1 = &serial1;
  20         };
  21
  22         memory@80000000 {
  23                 device_type = "memory";
  24                 reg = <0x00000000 0x80000000 0 0x80000000>;
  25                       /* DRAM space - 1, size : 2 GB DRAM */
  26         };
  27
  28         sysclk: sysclk {
  29                 compatible = "fixed-clock";
  30                 #clock-cells = <0>;
  31                 clock-frequency = <100000000>;
  32                 clock-output-names = "sysclk";
  33         };
  34
  35         gic: interrupt-controller@6000000 {
  36                 compatible = "arm,gic-v3";
  37                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  38                       <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
  39                 #interrupt-cells = <3>;
  40                 interrupt-controller;
  41                 interrupts = <1 9 0x4>;
  42         };
  43
  44         timer {
  45                 compatible = "arm,armv8-timer";
  46                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  47                              <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  48                              <1 11 0x8>, /* Virtual PPI, active-low */
  49                              <1 10 0x8>; /* Hypervisor PPI, active-low */
  50         };
  51
  52         soc {
  53                 compatible = "simple-bus";
  54                 #address-cells = <2>;
  55                 #size-cells = <2>;
  56                 ranges;
  57                 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
  58
  59                 clockgen: clocking@1300000 {
  60                         compatible = "fsl,ls2080a-clockgen";
  61                         reg = <0 0x1300000 0 0xa0000>;
  62                         #clock-cells = <2>;
  63                         clocks = <&sysclk>;
  64                 };
  65
  66                 serial0: serial@21c0500 {
  67                         compatible = "fsl,ns16550", "ns16550a";
  68                         reg = <0x0 0x21c0500 0x0 0x100>;
  69                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
  70                                             QORIQ_CLK_PLL_DIV(4)>;
  71                         interrupts = <0 32 0x4>; /* Level high type */
  72                         bootph-all;
  73                 };
  74
  75                 serial1: serial@21c0600 {
  76                         compatible = "fsl,ns16550", "ns16550a";
  77                         reg = <0x0 0x21c0600 0x0 0x100>;
  78                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
  79                                             QORIQ_CLK_PLL_DIV(4)>;
  80                         interrupts = <0 32 0x4>; /* Level high type */
  81                         bootph-all;
  82                 };
  83         };
  84
  85         i2c0: i2c@2000000 {
  86                 status = "disabled";
  87                 compatible = "fsl,vf610-i2c";
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90                 reg = <0x0 0x2000000 0x0 0x10000>;
  91                 interrupts = <0 34 0x4>; /* Level high type */
  92         };
  93
  94         i2c1: i2c@2010000 {
  95                 status = "disabled";
  96                 compatible = "fsl,vf610-i2c";
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99                 reg = <0x0 0x2010000 0x0 0x10000>;
 100                 interrupts = <0 34 0x4>; /* Level high type */
 101         };
 102
 103         i2c2: i2c@2020000 {
 104                 status = "disabled";
 105                 compatible = "fsl,vf610-i2c";
 106                 #address-cells = <1>;
 107                 #size-cells = <0>;
 108                 reg = <0x0 0x2020000 0x0 0x10000>;
 109                 interrupts = <0 35 0x4>; /* Level high type */
 110         };
 111
 112         i2c3: i2c@2030000 {
 113                 status = "disabled";
 114                 compatible = "fsl,vf610-i2c";
 115                 #address-cells = <1>;
 116                 #size-cells = <0>;
 117                 reg = <0x0 0x2030000 0x0 0x10000>;
 118                 interrupts = <0 35 0x4>; /* Level high type */
 119         };
 120
 121         dspi: dspi@2100000 {
 122                 compatible = "fsl,vf610-dspi";
 123                 #address-cells = <1>;
 124                 #size-cells = <0>;
 125                 reg = <0x0 0x2100000 0x0 0x10000>;
 126                 interrupts = <0 26 0x4>; /* Level high type */
 127                 spi-num-chipselects = <6>;
 128         };
 129
 130         qspi: quadspi@1550000 {
 131                 compatible = "fsl,ls2080a-qspi";
 132                 #address-cells = <1>;
 133                 #size-cells = <0>;
 134                 reg = <0x0 0x20c0000 0x0 0x10000>,
 135                         <0x0 0x20000000 0x0 0x10000000>;
 136                 reg-names = "QuadSPI", "QuadSPI-memory";
 137                 status = "disabled";
 138         };
 139
 140         esdhc: esdhc@0 {
 141                 compatible = "fsl,esdhc";
 142                 reg = <0x0 0x2140000 0x0 0x10000>;
 143                 interrupts = <0 28 0x4>; /* Level high type */
 144                 little-endian;
 145                 bus-width = <4>;
 146         };
 147
 148         gpio0: gpio@2300000 {
 149                 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 150                 reg = <0x0 0x2300000 0x0 0x10000>;
 151                 interrupts = <0 36 0x4>; /* Level high type */
 152                 gpio-controller;
 153                 little-endian;
 154                 #gpio-cells = <2>;
 155                 interrupt-controller;
 156                 #interrupt-cells = <2>;
 157         };
 158
 159         gpio1: gpio@2310000 {
 160                 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 161                 reg = <0x0 0x2310000 0x0 0x10000>;
 162                 interrupts = <0 36 0x4>; /* Level high type */
 163                 gpio-controller;
 164                 little-endian;
 165                 #gpio-cells = <2>;
 166                 interrupt-controller;
 167                 #interrupt-cells = <2>;
 168         };
 169
 170         gpio2: gpio@2320000 {
 171                 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 172                 reg = <0x0 0x2320000 0x0 0x10000>;
 173                 interrupts = <0 37 0x4>; /* Level high type */
 174                 gpio-controller;
 175                 little-endian;
 176                 #gpio-cells = <2>;
 177                 interrupt-controller;
 178                 #interrupt-cells = <2>;
 179         };
 180
 181         gpio3: gpio@2330000 {
 182                 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 183                 reg = <0x0 0x2330000 0x0 0x10000>;
 184                 interrupts = <0 37 0x4>; /* Level high type */
 185                 gpio-controller;
 186                 little-endian;
 187                 #gpio-cells = <2>;
 188                 interrupt-controller;
 189                 #interrupt-cells = <2>;
 190         };
 191
 192         usb0: usb3@3100000 {
 193                 compatible = "fsl,layerscape-dwc3";
 194                 reg = <0x0 0x3100000 0x0 0x10000>;
 195                 interrupts = <0 80 0x4>; /* Level high type */
 196                 dr_mode = "host";
 197         };
 198
 199         usb1: usb3@3110000 {
 200                 compatible = "fsl,layerscape-dwc3";
 201                 reg = <0x0 0x3110000 0x0 0x10000>;
 202                 interrupts = <0 81 0x4>; /* Level high type */
 203                 dr_mode = "host";
 204         };
 205
 206         pcie1: pcie@3400000 {
 207                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 208                 reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 209                        0x00 0x03480000 0x0 0x80000   /* lut registers */
 210                        0x10 0x00000000 0x0 0x20000>; /* configuration space */
 211                 reg-names = "dbi", "lut", "config";
 212                 #address-cells = <3>;
 213                 #size-cells = <2>;
 214                 device_type = "pci";
 215                 num-lanes = <4>;
 216                 bus-range = <0x0 0xff>;
 217                 ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000   /* downstream I/O */
 218                           0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 219         };
 220
 221         pcie2: pcie@3500000 {
 222                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 223                 reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 224                        0x00 0x03580000 0x0 0x80000   /* lut registers */
 225                        0x12 0x00000000 0x0 0x20000>; /* configuration space */
 226                 reg-names = "dbi", "lut", "config";
 227                 #address-cells = <3>;
 228                 #size-cells = <2>;
 229                 device_type = "pci";
 230                 num-lanes = <4>;
 231                 bus-range = <0x0 0xff>;
 232                 ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000   /* downstream I/O */
 233                           0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 234         };
 235
 236         pcie3: pcie@3600000 {
 237                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 238                 reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 239                        0x00 0x03680000 0x0 0x80000   /* lut registers */
 240                        0x14 0x00000000 0x0 0x20000>; /* configuration space */
 241                 reg-names = "dbi", "lut", "config";
 242                 #address-cells = <3>;
 243                 #size-cells = <2>;
 244                 device_type = "pci";
 245                 num-lanes = <8>;
 246                 bus-range = <0x0 0xff>;
 247                 ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000   /* downstream I/O */
 248                           0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 249         };
 250
 251         pcie4: pcie@3700000 {
 252                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 253                 reg = <0x00 0x03700000 0x0 0x80000   /* dbi registers */
 254                        0x00 0x03780000 0x0 0x80000   /* lut registers */
 255                        0x16 0x00000000 0x0 0x20000>; /* configuration space */
 256                 reg-names = "dbi", "lut", "config";
 257                 #address-cells = <3>;
 258                 #size-cells = <2>;
 259                 device_type = "pci";
 260                 num-lanes = <4>;
 261                 bus-range = <0x0 0xff>;
 262                 ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000   /* downstream I/O */
 263                           0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 264         };
 265
 266         sata: sata@3200000 {
 267                         compatible = "fsl,ls2080a-ahci";
 268                         reg = <0x0 0x3200000 0x0 0x10000>;
 269                         interrupts = <0 133 0x4>; /* Level high type */
 270                         status = "disabled";
 271         };
 272
 273         crypto: crypto@8000000 {
 274                 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 275                 fsl,sec-era = <8>;
 276                 #address-cells = <1>;
 277                 #size-cells = <1>;
 278                 ranges = <0x0 0x00 0x8000000 0x100000>;
 279                 reg = <0x00 0x8000000 0x0 0x100000>;
 280                 interrupts = <0 139 0x4>;  /* Level high type */
 281                 dma-coherent;
 282
 283                 sec_jr0: jr@10000 {
 284                         compatible = "fsl,sec-v5.0-job-ring",
 285                                      "fsl,sec-v4.0-job-ring";
 286                         reg        = <0x10000 0x10000>;
 287                         interrupts = <0 140 0x4>;  /* Level high type */
 288                 };
 289
 290                 sec_jr1: jr@20000 {
 291                         compatible = "fsl,sec-v5.0-job-ring",
 292                                      "fsl,sec-v4.0-job-ring";
 293                         reg        = <0x20000 0x10000>;
 294                         interrupts = <0 141 0x4>;  /* Level high type */
 295                 };
 296
 297                 sec_jr2: jr@30000 {
 298                         compatible = "fsl,sec-v5.0-job-ring",
 299                                      "fsl,sec-v4.0-job-ring";
 300                         reg        = <0x30000 0x10000>;
 301                         interrupts = <0 142 0x4>;  /* Level high type */
 302                 };
 303
 304                 sec_jr3: jr@40000 {
 305                         compatible = "fsl,sec-v5.0-job-ring",
 306                                      "fsl,sec-v4.0-job-ring";
 307                         reg        = <0x40000 0x10000>;
 308                         interrupts = <0 143 0x4>;  /* Level high type */
 309                 };
 310         };
 311
 312         fsl_mc: fsl-mc@80c000000 {
 313                 compatible = "fsl,qoriq-mc", "simple-mfd";
 314                 reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 315                       <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 316                 #address-cells = <3>;
 317                 #size-cells = <1>;
 318
 319                 /*
 320                  * Region type 0x0 - MC portals
 321                  * Region type 0x1 - QBMAN portals
 322                  */
 323                 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 324                         0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 325
 326                 dpmacs {
 327                         compatible = "simple-mfd";
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330
 331                         dpmac1: dpmac@1 {
 332                                 compatible = "fsl,qoriq-mc-dpmac";
 333                                 reg = <0x1>;
 334                                 status = "disabled";
 335                         };
 336
 337                         dpmac2: dpmac@2 {
 338                                 compatible = "fsl,qoriq-mc-dpmac";
 339                                 reg = <0x2>;
 340                                 status = "disabled";
 341                         };
 342
 343                         dpmac3: dpmac@3 {
 344                                 compatible = "fsl,qoriq-mc-dpmac";
 345                                 reg = <0x3>;
 346                                 status = "disabled";
 347                         };
 348
 349                         dpmac4: dpmac@4 {
 350                                 compatible = "fsl,qoriq-mc-dpmac";
 351                                 reg = <0x4>;
 352                                 status = "disabled";
 353                         };
 354
 355                         dpmac5: dpmac@5 {
 356                                 compatible = "fsl,qoriq-mc-dpmac";
 357                                 reg = <0x5>;
 358                                 status = "disabled";
 359                         };
 360
 361                         dpmac6: dpmac@6 {
 362                                 compatible = "fsl,qoriq-mc-dpmac";
 363                                 reg = <0x6>;
 364                                 status = "disabled";
 365                         };
 366
 367                         dpmac7: dpmac@7 {
 368                                 compatible = "fsl,qoriq-mc-dpmac";
 369                                 reg = <0x7>;
 370                                 status = "disabled";
 371                         };
 372
 373                         dpmac8: dpmac@8 {
 374                                 compatible = "fsl,qoriq-mc-dpmac";
 375                                 reg = <0x8>;
 376                                 status = "disabled";
 377                         };
 378                 };
 379         };
 380
 381         emdio1: mdio@8B96000 {
 382                 compatible = "fsl,ls-mdio";
 383                 reg = <0x0 0x8B96000 0x0 0x1000>;
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 status = "disabled";
 387         };
 388
 389         emdio2: mdio@8B97000 {
 390                 compatible = "fsl,ls-mdio";
 391                 reg = <0x0 0x8B97000 0x0 0x1000>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 status = "disabled";
 395         };
 396 };