arch/arm/dts/imx8mm-venice.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2021 Gateworks Corporation
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx8mm.dtsi"
   9
  10 / {
  11         model = "Gateworks Venice i.MX8MM board";
  12         compatible = "gw,imx8mm-venice", "fsl,imx8mm";
  13
  14         chosen {
  15                 stdout-path = &uart2;
  16         };
  17
  18         memory@40000000 {
  19                 device_type = "memory";
  20                 reg = <0x0 0x40000000 0 0x80000000>;
  21         };
  22 };
  23
  24 &i2c1 {
  25         clock-frequency = <100000>;
  26         pinctrl-names = "default";
  27         pinctrl-0 = <&pinctrl_i2c1>;
  28         status = "okay";
  29
  30         gsc: gsc@20 {
  31                 compatible = "gw,gsc";
  32                 reg = <0x20>;
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35         };
  36
  37         eeprom@51 {
  38                 compatible = "atmel,24c02";
  39                 reg = <0x51>;
  40                 pagesize = <16>;
  41         };
  42 };
  43
  44 &i2c2 {
  45         clock-frequency = <400000>;
  46         pinctrl-names = "default";
  47         pinctrl-0 = <&pinctrl_i2c2>;
  48         status = "okay";
  49
  50         eeprom@52 {
  51                 compatible = "atmel,24c32";
  52                 reg = <0x52>;
  53                 pagesize = <32>;
  54         };
  55 };
  56
  57 /* console */
  58 &uart2 {
  59         pinctrl-names = "default";
  60         pinctrl-0 = <&pinctrl_uart2>;
  61         status = "okay";
  62 };
  63
  64 /* eMMC */
  65 &usdhc3 {
  66         assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
  67         assigned-clock-rates = <400000000>;
  68         pinctrl-names = "default", "state_100mhz", "state_200mhz";
  69         pinctrl-0 = <&pinctrl_usdhc3>;
  70         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  71         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  72         bus-width = <8>;
  73         non-removable;
  74         status = "okay";
  75 };
  76
  77 &wdog1 {
  78         pinctrl-names = "default";
  79         pinctrl-0 = <&pinctrl_wdog>;
  80         fsl,ext-reset-output;
  81         status = "okay";
  82 };
  83
  84 &iomuxc {
  85         pinctrl_i2c1: i2c1grp {
  86                 fsl,pins = <
  87                         MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
  88                         MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
  89                 >;
  90         };
  91
  92         pinctrl_i2c2: i2c2grp {
  93                 fsl,pins = <
  94                         MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3
  95                         MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3
  96                 >;
  97         };
  98
  99         pinctrl_uart2: uart2grp {
 100                 fsl,pins = <
 101                         MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 102                         MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 103                 >;
 104         };
 105
 106         pinctrl_usdhc3: usdhc3grp {
 107                 fsl,pins = <
 108                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x190
 109                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d0
 110                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d0
 111                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d0
 112                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d0
 113                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d0
 114                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d0
 115                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d0
 116                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d0
 117                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d0
 118                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x190
 119                 >;
 120         };
 121
 122         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 123                 fsl,pins = <
 124                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194
 125                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4
 126                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4
 127                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4
 128                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4
 129                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4
 130                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d4
 131                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d4
 132                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d4
 133                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d4
 134                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x194
 135                 >;
 136         };
 137
 138         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 139                 fsl,pins = <
 140                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196
 141                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6
 142                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6
 143                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6
 144                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6
 145                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6
 146                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d6
 147                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d6
 148                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d6
 149                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d6
 150                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x196
 151                 >;
 152         };
 153
 154         pinctrl_wdog: wdoggrp {
 155                 fsl,pins = <
 156                         MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0xc6
 157                 >;
 158         };
 159 };