1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/ti-serdes.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include "k3-am642.dtsi"
12 #include "k3-am64-sk-lp4-1600MTs.dtsi"
13 #include "k3-am64-ddr.dtsi"
17 stdout-path = "serial2:115200n8";
22 remoteproc0 = &sysctrler;
27 device_type = "memory";
29 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
34 compatible = "ti,am654-rproc";
35 reg = <0x00 0x00a90000 0x00 0x10>;
36 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
37 <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
38 resets = <&k3_reset 135 0>;
39 clocks = <&k3_clks 61 0>;
40 assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
41 assigned-clock-parents = <&k3_clks 61 2>;
42 assigned-clock-rates = <200000000>, <1000000000>;
44 ti,sci-proc-id = <32>;
45 ti,sci-host-id = <10>;
54 secure_ddr: optee@9e800000 {
55 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
61 clk_200mhz: dummy-clock-200mhz {
62 compatible = "fixed-clock";
64 clock-frequency = <200000000>;
70 sysctrler: sysctrler {
71 compatible = "ti,am654-system-controller";
72 mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
73 mbox-names = "tx", "rx";
79 main_esm: esm@420000 {
80 compatible = "ti,j721e-esm";
81 reg = <0x0 0x420000 0x0 0x1000>;
82 ti,esm-pins = <160>, <161>;
89 mcu_esm: esm@4100000 {
90 compatible = "ti,j721e-esm";
91 reg = <0x0 0x4100000 0x0 0x1000>;
92 ti,esm-pins = <0>, <1>;
99 main_uart0_pins_default: main-uart0-pins-default {
101 pinctrl-single,pins = <
102 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
103 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
104 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
105 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
109 main_uart1_pins_default: main-uart1-pins-default {
111 pinctrl-single,pins = <
112 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
113 AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
114 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
115 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
119 main_mmc1_pins_default: main-mmc1-pins-default {
121 pinctrl-single,pins = <
122 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
123 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
124 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
125 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
126 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
127 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
128 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
129 AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
133 main_usb0_pins_default: main-usb0-pins-default {
135 pinctrl-single,pins = <
136 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
140 mdio1_pins_default: mdio1-pins-default {
141 pinctrl-single,pins = <
142 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
143 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
147 rgmii1_pins_default: rgmii1-pins-default {
148 pinctrl-single,pins = <
149 AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
150 AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
151 AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
152 AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
153 AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
154 AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
155 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
156 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
157 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
158 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
159 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
160 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
164 rgmii2_pins_default: rgmii2-pins-default {
165 pinctrl-single,pins = <
166 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
167 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
168 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
169 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
170 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
171 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
172 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
173 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
174 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
175 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
176 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
177 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
183 mboxes= <&secure_proxy_main 0>,
184 <&secure_proxy_main 1>,
185 <&secure_proxy_main 0>;
186 mbox-names = "rx", "tx", "notify";
192 /delete-property/ power-domains;
193 /delete-property/ clocks;
194 /delete-property/ clock-names;
195 pinctrl-names = "default";
196 pinctrl-0 = <&main_uart0_pins_default>;
202 pinctrl-names = "default";
203 pinctrl-0 = <&main_uart1_pins_default>;
207 /delete-property/ power-domains;
208 clocks = <&clk_200mhz>;
209 clock-names = "clk_xin";
210 ti,driver-strength-ohm = <50>;
212 pinctrl-0 = <&main_mmc1_pins_default>;
216 idle-states = <AM64_SERDES0_LANE0_USB>;
224 serdes0_usb_link: link@0 {
226 cdns,num-lanes = <1>;
228 cdns,phy-type = <PHY_TYPE_USB3>;
229 resets = <&serdes_wiz0 1>;
239 maximum-speed = "super-speed";
240 pinctrl-names = "default";
241 pinctrl-0 = <&main_usb0_pins_default>;
242 phys = <&serdes0_usb_link>;
243 phy-names = "cdns3,usb3-phy";
247 pinctrl-names = "default";
248 pinctrl-0 = <&mdio1_pins_default
250 &rgmii2_pins_default>;
254 phy-mode = "rgmii-rxid";
255 phy-handle = <&cpsw3g_phy1>;
259 cpsw3g_phy1: ethernet-phy@1 {
261 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
262 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
266 #include "k3-am642-sk-u-boot.dtsi"