arch/arm/dts/k3-j721s2-r5-common-proc-board.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "k3-j721s2-som-p0.dtsi"
   9 #include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
  10 #include "k3-j721s2-ddr.dtsi"
  11
  12 / {
  13         chosen {
  14                 firmware-loader = &fs_loader0;
  15                 stdout-path = &main_uart8;
  16                 tick-timer = &timer1;
  17         };
  18
  19         aliases {
  20                 remoteproc0 = &sysctrler;
  21                 remoteproc1 = &a72_0;
  22         };
  23
  24         fs_loader0: fs_loader@0 {
  25                 compatible = "u-boot,fs-loader";
  26                 bootph-all;
  27         };
  28
  29         a72_0: a72@0 {
  30                 compatible = "ti,am654-rproc";
  31                 reg = <0x0 0x00a90000 0x0 0x10>;
  32                 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
  33                                 <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
  34                 resets = <&k3_reset 202 0>;
  35                 clocks = <&k3_clks 61 1>;
  36                 assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
  37                 assigned-clock-parents = <&k3_clks 61 2>;
  38                 assigned-clock-rates = <200000000>, <2000000000>;
  39                 ti,sci = <&sms>;
  40                 ti,sci-proc-id = <32>;
  41                 ti,sci-host-id = <10>;
  42                 bootph-pre-ram;
  43         };
  44
  45         clk_200mhz: dummy_clock_200mhz {
  46                 compatible = "fixed-clock";
  47                 #clock-cells = <0>;
  48                 clock-frequency = <200000000>;
  49                 bootph-pre-ram;
  50         };
  51
  52         clk_19_2mhz: dummy_clock_19_2mhz {
  53                 compatible = "fixed-clock";
  54                 #clock-cells = <0>;
  55                 clock-frequency = <19200000>;
  56                 bootph-pre-ram;
  57         };
  58 };
  59
  60 &cbass_mcu_wakeup {
  61         sa3_secproxy: secproxy@44880000 {
  62                 bootph-pre-ram;
  63                 compatible = "ti,am654-secure-proxy";
  64                 reg = <0x0 0x44880000 0x0 0x20000>,
  65                       <0x0 0x44860000 0x0 0x20000>,
  66                       <0x0 0x43600000 0x0 0x10000>;
  67                 reg-names = "rt", "scfg", "target_data";
  68                 #mbox-cells = <1>;
  69         };
  70
  71         mcu_secproxy: secproxy@2a380000 {
  72                 compatible = "ti,am654-secure-proxy";
  73                 reg = <0x0 0x2a380000 0x0 0x80000>,
  74                       <0x0 0x2a400000 0x0 0x80000>,
  75                       <0x0 0x2a480000 0x0 0x80000>;
  76                 reg-names = "rt", "scfg", "target_data";
  77                 #mbox-cells = <1>;
  78                 bootph-pre-ram;
  79         };
  80
  81         sysctrler: sysctrler {
  82                 compatible = "ti,am654-system-controller";
  83                 mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
  84                 mbox-names = "tx", "rx", "boot_notify";
  85                 bootph-pre-ram;
  86         };
  87
  88         dm_tifs: dm-tifs {
  89                 compatible = "ti,j721e-dm-sci";
  90                 ti,host-id = <3>;
  91                 ti,secure-host;
  92                 mbox-names = "rx", "tx";
  93                 mboxes= <&mcu_secproxy 21>,
  94                         <&mcu_secproxy 23>;
  95                 bootph-pre-ram;
  96         };
  97 };
  98
  99 &main_pmx0 {
 100         main_uart8_pins_default: main-uart8-pins-default {
 101                 pinctrl-single,pins = <
 102                         J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
 103                         J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
 104                         J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
 105                         J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
 106                 >;
 107         };
 108
 109         main_mmc1_pins_default: main-mmc1-pins-default {
 110                 pinctrl-single,pins = <
 111                         J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
 112                         J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
 113                         J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
 114                         J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
 115                         J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
 116                         J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
 117                         J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
 118                         J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
 119                 >;
 120         };
 121 };
 122
 123 &wkup_pmx0 {
 124         mcu_uart0_pins_default: mcu-uart0-pins-default {
 125                 bootph-pre-ram;
 126                 pinctrl-single,pins = <
 127                         J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */
 128                         J721S2_WKUP_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
 129                         J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
 130                         J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
 131                 >;
 132         };
 133
 134         wkup_uart0_pins_default: wkup-uart0-pins-default {
 135                 bootph-pre-ram;
 136                 pinctrl-single,pins = <
 137                         J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
 138                         J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
 139                         J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
 140                         J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
 141                 >;
 142         };
 143 };
 144
 145 &sms {
 146         mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
 147         mbox-names = "tx", "rx", "notify";
 148         ti,host-id = <4>;
 149         ti,secure-host;
 150         bootph-pre-ram;
 151 };
 152
 153 &wkup_uart0 {
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&wkup_uart0_pins_default>;
 156 };
 157
 158 &mcu_uart0 {
 159         pinctrl-names = "default";
 160         pinctrl-0 = <&mcu_uart0_pins_default>;
 161 };
 162
 163 &main_uart8 {
 164         pinctrl-names = "default";
 165         pinctrl-0 = <&main_uart8_pins_default>;
 166 };
 167
 168 &main_sdhci0 {
 169         /delete-property/ power-domains;
 170         /delete-property/ assigned-clocks;
 171         /delete-property/ assigned-clock-parents;
 172         clock-names = "clk_xin";
 173         clocks = <&clk_200mhz>;
 174         ti,driver-strength-ohm = <50>;
 175         non-removable;
 176         bus-width = <8>;
 177 };
 178
 179 &main_sdhci1 {
 180         /delete-property/ power-domains;
 181         /delete-property/ assigned-clocks;
 182         /delete-property/ assigned-clock-parents;
 183         pinctrl-0 = <&main_mmc1_pins_default>;
 184         pinctrl-names = "default";
 185         clock-names = "clk_xin";
 186         clocks = <&clk_200mhz>;
 187         ti,driver-strength-ohm = <50>;
 188 };
 189
 190 &mcu_ringacc {
 191         ti,sci = <&dm_tifs>;
 192 };
 193
 194 &mcu_udmap {
 195         ti,sci = <&dm_tifs>;
 196 };
 197
 198 #include "k3-j721s2-common-proc-board-u-boot.dtsi"