arch/arm/dts/ls1021a-twr.dtsi

   1 /*
   2  * Freescale ls1021a TWR board common device tree source
   3  *
   4  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include "ls1021a.dtsi"
  10
  11 / {
  12         model = "LS1021A TWR Board";
  13
  14         aliases {
  15                 enet2_rgmii_phy = &rgmii_phy1;
  16                 enet0_sgmii_phy = &sgmii_phy2;
  17                 enet1_sgmii_phy = &sgmii_phy0;
  18                 spi0 = &qspi;
  19                 spi1 = &dspi1;
  20         };
  21
  22         chosen {
  23                 stdout-path = &uart0;
  24         };
  25 };
  26
  27 &qspi {
  28         bus-num = <0>;
  29         status = "okay";
  30
  31         qflash0: n25q128a13@0 {
  32                 #address-cells = <1>;
  33                 #size-cells = <1>;
  34                 compatible = "spi-flash";
  35                 spi-max-frequency = <20000000>;
  36                 reg = <0>;
  37         };
  38 };
  39
  40 &dspi1 {
  41         bus-num = <0>;
  42         status = "okay";
  43
  44         dspiflash: at26df081a@0 {
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47                 compatible = "spi-flash";
  48                 spi-max-frequency = <16000000>;
  49                 spi-cpol;
  50                 spi-cpha;
  51                 reg = <0>;
  52         };
  53 };
  54
  55 &i2c0 {
  56         status = "okay";
  57 };
  58
  59 &i2c1 {
  60         status = "okay";
  61 };
  62
  63 &ifc {
  64         #address-cells = <2>;
  65         #size-cells = <1>;
  66         /* NOR Flash on board */
  67         ranges = <0x0 0x0 0x60000000 0x08000000>;
  68         status = "okay";
  69
  70         nor@0,0 {
  71                 #address-cells = <1>;
  72                 #size-cells = <1>;
  73                 compatible = "cfi-flash";
  74                 reg = <0x0 0x0 0x8000000>;
  75                 bank-width = <2>;
  76                 device-width = <1>;
  77         };
  78 };
  79
  80 &lpuart0 {
  81         status = "okay";
  82 };
  83
  84 &mdio0 {
  85         sgmii_phy0: ethernet-phy@0 {
  86                 reg = <0x0>;
  87         };
  88         rgmii_phy1: ethernet-phy@1 {
  89                 reg = <0x1>;
  90         };
  91         sgmii_phy2: ethernet-phy@2 {
  92                 reg = <0x2>;
  93         };
  94         tbi1: tbi-phy@1f {
  95                 reg = <0x1f>;
  96                 device_type = "tbi-phy";
  97         };
  98 };
  99
 100 &uart0 {
 101         status = "okay";
 102 };
 103
 104 &uart1 {
 105         status = "okay";
 106 };